mma2602wr2 Freescale Semiconductor, Inc, mma2602wr2 Datasheet - Page 33
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mma2602wr2
Manufacturer Part Number
mma2602wr2
Description
Dsi Inertial Sensor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MMA2602WR2.pdf
(48 pages)
4.2.1.3
The data bits D[7:0] in the command are only used in the CRC calculation.
Table 22. Read Acceleration Data Command Bit Definitions
Table 24. Long Response - Read Acceleration Data Command
Table 25. Read Acceleration Response Bit Definitions
minimum acceleration value is transmitted as defined in
Sensors
Freescale Semiconductor
Table 21. Read Acceleration Data Command
Table 23. Short Response - Read Acceleration Data Command
Response
D[15]
D[7]
A[3]
The Read Acceleration Data command is supported in the following command formats:
The device ignores the Request Status command if the DSI device address is set to the DSI Global Device Address of ‘0000’.
Length
The device truncates the LSBs for Acceleration Data Responses of length less than 10. If the result of the truncation is 0, the
⎯
AT_OTP[1:0]
Bit Field
10
11
12
13
14
15
Bit Field
8
9
AD[9:0]
C[3:0]
A[3:0]
D[7:0]
A[3:0]
ST
S
D[14]
D[6]
A[2]
⎯
AT_OTP[1]
• Standard Long Command
• Standard Short Command
• Enhanced Long Command as configured by the Format Control Command (Reference
• Enhanced Short Command as configured by the Form at Control Command (Reference
D[14]
Read Acceleration Data Command
D[13]
D[5]
A[1]
⎯
Read Acceleration Data Command = ‘0010’
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
Used for CRC calculation only
Ten-bit acceleration result produced by the device.
This bit indicates whether the device has detected an internal device error.
1 - Internal Error detected.
0 - No Internal Error detected
Reference
This bit indicates whether internal self-test circuitry is active
1 - Self-test active
0 - Self-test disabled
DSI device address. This field contains the device address.
Attribute bits located in Register DEVCFG1 (Reference
Shaded bits are transmitted to meet the response message length of the received message
AT_OTP[0]
D[13]
D[12]
D[4]
A[0]
⎯
Data
Table 59
D[11]
D[12] D[11] D[10]
D[3]
⎯
ST
0
for conditions that set the S bit.
D[10]
D[2]
⎯
0
S
AD[9]
D[1]
D[9]
S
⎯
AD[9]
D[9]
AD[8]
D[0]
D[8]
Response
⎯
Table
AD[9]
AD[8]
D[8]
Response
AD[7]
A[3]
D[7]
A[3]
26.
Section
AD[9]
AD[8]
AD[7]
D[7]
AD[6]
A[2]
D[6]
A[2]
Definition
Definition
3.1.4.2)
Address
AD[8]
AD[7]
AD[6]
D[6]
AD[5]
A[1]
D[5]
A[1]
AD[7]
AD[6]
AD[5]
D[5]
AD[4]
A[0]
D[4]
A[0]
AD[6]
AD[5]
AD[4]
D[4]
AD[3]
C[3]
D[3]
0
AD[5]
AD[4]
AD[3]
D[3]
AD[2]
C[2]
D[2]
Command
0
AD[4]
AD[3]
AD[2]
D[2]
Section 4.2.1.11
AD[1]
Section 4.2.1.11
C[1]
D[1]
AD[3]
AD[2]
AD[1]
1
D[1]
AD[0]
C[0]
D[0]
AD[2]
AD[1]
AD[0]
D[0]
0
MMA26xxWR
)
)
0 to 8 bits
0 to 8 bits
0 to 8 bits
CRC
CRC
CRC
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