s908ey16g2vfar Freescale Semiconductor, Inc, s908ey16g2vfar Datasheet - Page 195

• Manufacturer Part Number: s908ey16g2vfar
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

SPWOM — SPI Wired-OR Mode Bit
SPE — SPI Enable Bit
SPTIE — SPI Transmit Interrupt Enable Bit
15.13.2 SPI Status and Control Register
The SPI status and control register contains flags to signal the following conditions:
The SPI status and control register also contains bits that perform these functions:
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the slave data register must be loaded with the desired transmit data before the falling edge of SS. Any
data written after the falling edge is stored in the data register and transferred to the shift register at
the current transmission.
When CPHA = 1 for a slave, the first edge of the SPSCK indicates the beginning of the transmission.
The same applies when SS is high for a slave. The MISO pin is held in a high-impedance state, and
the incoming SPSCK is ignored. In certain cases, it may also cause the MODF flag to be set. (See
15.6.2 Mode Fault
machine.
This read/write bit disables the pullup devices on pins SPSCK, MOSI, and MISO so that those pins
become open-drain outputs.
This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI (see
Resetting the
This read/write bit enables CPU interrupt requests generated by the SPTE bit. SPTE is set when a byte
transfers from the transmit data register to the shift register. Reset clears the SPTIE bit.
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1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins
1 = SPI module enabled
0 = SPI module disabled
1 = SPTE CPU interrupt requests enabled
0 = SPTE CPU interrupt requests disabled
Receive data register full
Failure to clear SPRF bit before next byte is received (overflow error)
Inconsistent logic level on SS pin (mode fault error)
Transmit data register empty
Enable error interrupts
Enable mode fault error detection
Select master SPI baud rate
Address:
Reset:
Read:
Write:
SPI). Reset clears the SPE bit.
Error). A logic 1 on the SS pin does not in any way affect the state of the SPI state
Figure 15-13. SPI Status and Control Register (SPSCR)
$000E
SPRF
Bit 7
0
MC68HC908EY16A • MC68HC908EY8A Data Sheet, Rev. 1
= Unimplemented
ERRIE
6
0
OVRF
5
0
MODF
4
0
SPTE
3
1
MODFEN
2
0
SPR1
1
0
SPR0
Bit 0
0
I/O Registers
15.9
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