s908ey16g2vfar Freescale Semiconductor, Inc, s908ey16g2vfar Datasheet - Page 96

• Manufacturer Part Number: s908ey16g2vfar
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Internal Clock Generator (ICG) Module
asynchronously to the clocks. The unpredictably of the transition period is a necessary result of the
asynchronicity.
The switch automatically selects ICLK during reset. When the clock monitor is on (CMON is set) and it
determines one of the clock sources is inactive (as indicated by the IOFF or EOFF signals), the circuit is
forced to select the active clock. There are no clocks for the inactive side of the synchronizer to properly
operate, so that side is forced deselected. However, the active side will not be selected until one to two
clock cycles after the IOFF or EOFF signal transitions.
8.4 Usage Notes
The ICG has several features which can provide protection to the microcontroller if properly used. Other
features can greatly simplify usage of the ICG if certain techniques are employed. This section describes
several possible ways to use the ICG and its features. These techniques are not the only ways to use the
ICG and may not be optimum for all environments. In any case, these techniques should be used only as
a template, and the user should modify them according to the application’s requirements.
These notes include:
8.4.1 Switching Clock Sources
Switching from one clock source to another requires both clock sources to be enabled and stable. A
simple flow requires:
The key point to remember in this flow is that the clock source cannot be switched (CS cannot be written)
unless the desired clock is on and stable.
8.4.2 Enabling the Clock Monitor
Many applications require the clock monitor to determine if one of the clock sources has become inactive,
so the other can be used to recover from a potentially dangerous situation. Using the clock monitor
requires both clocks to be active (ECGON and ICGON both set). To enable the clock monitor, both clocks
also must be stable (ECGS and ICGS both set). This is to prevent the use of the clock monitor when a
clock is first turned on and potentially unstable.
96
•
•
•
•
•
•
•
•
•
•
•
•
Switching clock sources
Enabling the clock monitor
Using clock monitor interrupts
Quantization error in digitally controlled oscillator (DCO) output
Switching internal clock frequencies
Nominal frequency settling time
Improving frequency settling time
Trimming frequency
Enable desired clock source
Wait for it to become stable
Switch clocks
Disable previous clock source
MC68HC908EY16A • MC68HC908EY8A Data Sheet, Rev. 1
Freescale Semiconductor