mt46v128m8p-6t Micron Semiconductor Products, mt46v128m8p-6t Datasheet - Page 74
mt46v128m8p-6t
Manufacturer Part Number
mt46v128m8p-6t
Description
1gb Ddr Sdram Component
Manufacturer
Micron Semiconductor Products
Datasheet
1.MT46V128M8P-6T.pdf
(82 pages)
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Figure 46:
PDF: 09005aef80a2f898/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
Command
BA0, BA1
Address
DQS
DQ
CK#
CKE
A10
DM
CK
5
t
t
IS
IS
Bank WRITE – Without Auto Precharge
NOP 1
T0
t
t
IH
IH
Notes:
t
t
Bank x
IS
IS
Row
Row
ACT
T1
1. NOP commands are shown for ease of illustration; other commands may be valid at these
2. BL = 4.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T8.
5. DI b = data-in from column b; subsequent elements are provided in the programmed order.
6. See Figure 48 on page 76 for detailed DQ timing.
t
t
IH
IH
times.
t
CK
t
t
RCD
RAS
NOP 1
T2
t
CH
t
CL
WRITE 2
t
Bank x
Col n
IS
3
T3
t
t
DQSS (NOM)
IH
t
WPRES
t DS
74
t
WPRE
NOP 1
T4
DI
b
t DH
T4n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
DQSL
NOP 1
T5
t
DQSH
T5n
1Gb: x4, x8, x16 DDR SDRAM
t
WPST
NOP 1
T6
Transitioning Data
©2003 Micron Technology, Inc. All rights reserved.
t
NOP 1
WR
T7
Operations
One bank
All banks
Don’t Care
Bank x 4
T8
PRE
t
RP
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