ics527-02 Integrated Device Technology, ics527-02 Datasheet - Page 2

• Manufacturer Part Number: ics527-02
• Description: Clock Slicer User Configurable Pecl Input Zero Delay Buffer
• Manufacturer: Integrated Device Technology

IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER 2
ICS527-02
CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER
Pin Assignment
Pin Descriptions
O E C L K 2
P E C L IN
P E C L IN
D IV 2
G N D
V D D
1,2, 24-28
R 5
R 6
Number
S 0
S 1
F 0
F 1
F 2
F 3
11-17
6, 23
9, 20
Pin
4, 5
10
18
19
21
22
3
7
8
28-pin 150 mil body SSOP
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
OECLK2
PECLIN
PECLIN
R5, R6,
Name
S0, S1
R0-R4
F0-F6
PDTS
CLK2
CLK1
FBIN
DIV2
GND
VDD
Pin
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
Output
Output
Power
Power
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Pin
R 4
R 3
R 2
R 1
R 0
V D D
C L K 1
C L K 2
G N D
P D T S
F B IN
F 6
F 5
F 4
Reference divider word input pins determined by user. Forms a binary number
from 0 to 127. Internal pull-up.
Selects CLK2 function to output a SYNC signal or a divide by 2 of CLK1 based
on the table above. Internal pull-up.
Select pins for output divider determined by user. See table above. Internal
pull-up.
Connect to +3.3 V.
True PECL input clock.
Complementary PECL input clock.
Connect to ground
CLK2 Output Enable. CLK2 tri-stated when low. Internal pull-up.
Feedback divider word input pins determined by user. Forms a binary number
from 0 to 127. Internal pull-up
Feedback clock input
Power Down. Active low. Turns off entire chip when low, both clock outputs are
tri-stated. Internal pull-up.
Output clock 2. Can be SYNC pulse or a low skew divide by 2 of CLK1.
Output clock 1.
Output Frequency Range Table
CLK2 Operation Table
S1 S0
OECLK2
0
0
1
1
0
1
1
0
1
0
1
Pin Description
Commercial
DIV2
20 -160
Output Frequency (MHz)
10 - 50
X
5 - 40
4 - 10
0
1
PECL ZDB AND MULTIPLIER/DIVIDER
CLK1/2
SYNC
CLK2
Industrial
Z
32 - 140
16 - 45
8 - 33
4 - 8
ICS527-02
REV H 092209