pc87307 National Semiconductor Corporation, pc87307 Datasheet - Page 26

• Manufacturer Part Number: pc87307
• Description: Plug And Play Compatible And Pc97 Compliant Superi/o
• Manufacturer: National Semiconductor Corporation

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2.3 THE CONFIGURATION REGISTERS
The configuration registers control the setup of the part.
Their major functions are to:
Section 2.3.2 summarizes information for each register of
each function. In addition, the following non-standard, or
card control registers are described in detail in Section 2.4,
starting on page 34.
•
•
•
•
•
•
•
Configuration within Parallel Port
Identify the chip
Enable major functions (such as, the Keyboard Control-
ler (KBC) for the keyboard and the mouse, the Real-
Time Clock (RTC), including Advanced Power Control
(APC), the Floppy Disc Controller (FDC), UARTs, paral-
lel and general purpose ports, power management and
pin functionality)
Define the I/O addresses of these functions
Define the status of these functions upon reset
Card Control Registers
— SuperI/O Configuration 1 Register (SIOC1)
— SuperI/O Configuration 2 Register (SIOC2)
— Programmable Chip Select Configuration Index
— Programmable Chip Select Configuration Data Reg-
KBC Configuration Register (Logical Device 0)
— SuperI/O KBC Configuration Register
FDC Configuration Registers (Logical Device 3)
— SuperI/O FDC Configuration Register
— Drive ID Register
a. The SuperI/O processor does not decode the Parallel Port outside this range.
Register
ister
No Internal Configuration
No Internal Configuration
EPP (Non ECP Mode 4)
Parallel Port Mode
ECP with Mode 4,
ECP with Mode 4,
ECP, No Mode 4,
SPP
TABLE 2-4. Parallel Port Address Range Allocation
Configuration Register Bits
SuperI/O Parallel Port
7
1
1
1
1
0
0
Configuration
6
0
1
0
1
0
1
or
5
x
0
1
0
1
x
26
4
x
0
0
1
1
x
•
•
•
•
Parallel Port Configuration Register (Logical Device 4)
— SuperI/O Parallel Port Configuration Register
UART2 and Infrared Configuration Register (Logical
Device 5)
— SuperI/O UART2 Configuration Register
UART1 Configuration Register (Logical Device 6)
— SuperI/O UART1 Configuration Register
Programmable Chip Select Configuration Registers
— CS0 Base Address MSB Register
— CS0 Base Address LSB Register
— CS0 Configuration Register
— CS1 Base Address MSB Register
— CS1 Base Address LSB Register
— CS1 Configuration Register
— CS2 Base Address MSB Register
— CS2 Base Address LSB Register
— CS2 Configuration Register
Three registers, from base to base + 02h
Eight registers, from base to base + 07h
Six registers, from base to base + 02h and
from base + 400h to base + 402h
11 registers, from base to base + 07h and
from base + 400h to base + 402h
16 registers, from base to base + 07h and
from base + 400h to base + 407h
Decoded Range
a