pc87307 National Semiconductor Corporation, pc87307 Datasheet - Page 61

• Manufacturer Part Number: pc87307
• Description: Plug And Play Compatible And Pc97 Compliant Superi/o
• Manufacturer: National Semiconductor Corporation

4.5.2
Bit 0 - Timer Match Enable (TME)
Bit 1 - RING Source Select (RSS)
Bit 2 - RING Pulse or Train Detection Mode (RPTDM)
Bit 3 - RING Enable (RE)
Bit 4 - RI1 Enable (R1E)
Bit 5 - RI2 Enable (R2E)
Bit 6 - Switch Off Delay Enable (SODE)
Bit 7 - Reserved
7
0 - Pre-determined date or time event is ignored.
1 - Match between the RTC and the pre-determined
0 - RING source is RING/XDCS signal, regardless of
1 - RING source is GPIO23/RING signal.
0 - Detection of RING pulse falling edge.
1 - Detection of RING pulse train above 16 Hz for 0.19
0 - RING input signal is ignored.
1 - RING detection activates the ONCTL output signal,
0 - RI1 input signal is ignored.
1 - A high to low transition on the RI1 input pin acti-
0 - RI2 input signal is ignored.
1 - A high to low transition on the RI2 input pin acti-
0 - ONCTL output pin is deactivated immediately after
1 - After the Switch Off Event, ONCTL output signal is
This bit is reserved.
6
Reserved
date and time activates the ONCTL output signal.
See MOAP (bit 4) of APCR1 for an overriding case.
X-bus Data Buffer (XDB) select bit of SuperI/O
Configuration 1 register.
sec.
unless it is overridden by the MOAP bit, bit 4 of the
APCR1 register.
vates the ONCTL output pin.
See MOAP (bit 4) of APCR1 for an overriding case.
vates the ONCTL output pin.
See MOAP (bit 4) of APCR1 for an overriding case.
the Switch Off event.
deactivated after a 5 or 21 second Switch Off delay.
APC Control Register 2 (APCR2), Index 41h
FIGURE 4-12. APCR2 Register Bitmap
5
SODE
4
R2E
3
R1E
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
2
RE
1
RPTDM
0
RSS
Power-Up
Reset
Required
TME
APC Control
Register 2
Index 41h
(APCR2)
61
4.5.3
Bits 5-0 in this register are cleared to 0, when this register
is read.
Bit 0 - Timer Match Detect (TMD)
Bit 1 - RING Detect (RID)
Bit 2 - RI1 Detect
Bit 3 - RI2 Detect
Bit 4 - Fail-Safe Timer Detect (FTD)
Bit 5 - Switch Off Event Detect (SOED)
Bit 6 - Reserved
Bit 7 - RING Status Bit (RS)
7
This bit is set to 1 when the RTC reaches the pre-deter-
mined date, regardless of the Timer Match Enable bit
(bit 0 of APCR2). After first Power-Up, the RTC and the
pre-determined date, are 0 and so this bit is set. It is rec-
ommended to clear this bit by reading this register after
first Power-Up.
This bit is set to 1 when a high to low transition is detect-
ed on the RING input pin and bit 2 of APCR2 is 0, or
when a RING pulse train is detected on the RING input
pin and bit 2 of APCR2 is 1, regardless of the status of
the RING enable bit.
This bit is set to 1 when a high to low transition is detect-
ed on the RI1 input signal, regardless of the RI1 Enable
bit.
This bit is set to 1 when a high to low transition is detect-
ed on the RI2 input pin, regardless of the RI2 Enable bit.
This bit is set to 1 when the Fail-safe timer reaches ter-
minal count.
This bit is set to 1 when a Switch Off event is detected,
regardless of the Switch Off Delay Enable bit.
Reserved.
Holds the instantaneous value of the selected RING pin.
RS
6
APC Status Register (APSR), Index 42h
Reserved
FIGURE 4-13. APSR Register Bitmap
5
0
SOED
4
0
FTD
3
0
0
2
RI2 Detect
RI1 Detect
0
1
1
RID
0
Power-Up
Reset
Required
TMD
APC Status
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Index 42h
Register
(APSR)