sy89537l Micrel Semiconductor, sy89537l Datasheet - Page 8

• Manufacturer Part Number: sy89537l
• Description: Sy89537l 3.3v Precision Lvpecl And Lvds Programmable Multiple Output Bank Clock Synthesizer And Fanout Buffer
• Manufacturer: Micrel Semiconductor

Micrel, Inc.
AC Electrical Characteristics
V
= 50Ω into V
Notes:
7.
8.
9.
10. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, T
11. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2
12. Total jitter definition: with an ideal clock input of frequency <f
13. Crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each
December 2007
Symbol
f
f
f
f
t
t
t
BW
t
t
t
t
CCA
IN
PHASE
OUT
VCO
SKEW
LOCK
JITTER
DC
r,
PW_SYNC_MIN
PD_SYNC
t
f
Fundamental mode, series resonant crystal.
The bank-to-bank skew is defined as the worst-case difference between any two similar delay paths within a single device operating at the
same voltage and temperature.
Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at
the respective inputs.
output signal.
than the specified peak-to-peak jitter value.
other at the inputs.
= V
CCD
= +3.3V ±10%; V
CCO
Parameter
XTAL Input Frequency Range
Reference Input Frequency Range
Phase Detector Operating Frequency Range
Output Frequency Range
Internal VCO Frequency Range
LVPECL Output Banks (0–3), Bank-to-Bank
LVDS Output Banks (0–2), Bank-to-Bank
Part-to-Part Skew
PLL Lock Time
Loop Filter Optimized for Cycle-to-Cycle Jitter
• R = 130_
• C1 = 0.47µF
• C2 = 100pF
1-Sigma Cycle-to-Cycle Jitter (XTAL Reference)
1-Sigma Cycle-to-Cycle Jitter (RFCK Reference)
Deterministic Jitter
Total Jitter
Spur
XTAL/RFCK Crosstalk-Induced Jitter
PLL Bandwidth
F
Output Rise/Fall Time (20% to 80%) LVPECL
Output Rise/Fall Time (20% to 80%) LVDS
–2V; T
OUT
Duty Cycle
A
= –40°C to +85°C, unless otherwise stated.
CCO
= +2.5V ±5% or +3.3V ±10%, R
MAX
, no more than one output edge in 10
23
-1 PRBS pattern.
8
Condition
Note 7
Note 8
Note 9
Note 10
Note 10
Note 11
Note 12
Note 13
See “PLL Stability” Table
See “Synchronization”
See “Synchronization”
L
(LVDS) = 100Ω across the output, R
n
– T
n-1
where T is the time between rising edges of the
[e-mail]
12
2352
output edges will deviate by more
73.5
28.8
Min
100
14
14
14
43
80
8
Typ
250
150
5.5
-35
15
15
80
50
4
5
8
M9999-121207-B
or [phone]
L
3024
Max
99.8
144
756
200
100
400
300
0.7
18
18
50
50
10
57
(LVPECL)
6
7
8
SY89537L
Internal
Internal
ps
ps
ps
Units
clock
cycle
clock
cycle
MHz
MHz
MHz
MHz
MHz
ps
ps
dBc@
fphase
kHz
ms
ps
ps
ps
ps
ps
%
RMS
RMS
RMS
PP
PP