mc88920 Integrated Device Technology, mc88920 Datasheet
mc88920
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mc88920 Summary of contents
Page 1
... The PLL allows the the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple locations on a board. The PLL also allows the MC88920 to multiply a low frequency input clock and distribute it locally at a higher (2X) system frequency ...
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... MC88920 Low Skew CMOS PLL Clock Drivers With Power-Down/Power-up Feature MC88920 Power–Down Mode Functionality The MC88920 has a special feature designed in to allow the processor clock inputs to be reset for total processor power–down, and then to return to phase–locked operation very quickly when the processor is powered– ...
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... Unit Condition V V OUT = 0. – 0. OUT = 0. – 0. –36mA –36mA +36mA +36mA GND – 2. OLD = 1.0V Max mA V OHD = 3.85 Min GND MC88920 MOTOROLA ...
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... IDT™ Low Skew CMOS PLL Clock Drivers With Power-Down/Power-up Feature MOTOROLA Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor, Inc. RC1 CH VCO PUMP Figure 1. MC88920 Logic Block Diagram Parameter 5%) Parameter For More Information On This Product to: www.freescale.com 4 RST_OUT 2X_Q D ...
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... Terminated (See Timing Diagram in Figure 13.5 ns Into a 50 Load Terminated — Clock Cycles ns (Q Frequency) — ns — ns When in Phase–Lock 16.5 ns See Application Note 5 1024 ‘Q’ Cycles ns See Application (512 Q/2 Cycles) Note 5 MOTOROLA NETCOM MC88920 ...
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... However, to correctly predict the skew from a given output on one part to any other output on one or more other parts, the distribution of each output in relation to the SYNC input must be known. This distribution for the MC88920 is provided in Table 1. TABLE 1. Distribution of Each Output versus SYNC Output ...
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... Q/2 Output Figure 6. Output/Input Switching Waveforms and Timing Relationships 1. The MC88920 aligns rising edges of the outputs and the SYNC input, therefore the SYNC input does not require a 50% duty cycle. 2. All skew specs are measured between the crossing point of the appropriate output edges. All skews are specified as ‘ ...
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... FREQ BIAS 0.1 F (LOOP FILTER CAP SEPARATE ANALOG POWER SUPPLY IS NOT NECESSARY AND SHOULD NOT BE USED. FOLLOWING THESE PRESCRIBED GUIDE- BOARD GND LINES IS ALL THAT IS NECESSARY TO USE THE MC88920 IN A NORMAL DIGITAL ENVIRONMENT. For More Information On This Product to: www.freescale.com 8 5 ANALOG V CC ...
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... Low Skew CMOS PLL Clock Drivers With Power-Down/Power-up Feature 12.5MHz X–TAL OSCILLATOR SYSTEM RESET Figure 8. Typical MC88920/MC68040 System Configuration IDT™ Low Skew CMOS PLL Clock Drivers With Power-Down/Power-up Feature TIMING SOLUTIONS Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc BR1333 — REV 5 Freescale Semiconductor, Inc ...
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... MILLIMETERS INCHES DIM MIN MAX MIN MAX A 12.65 12.95 0.499 0.510 B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019 F 0.50 0.90 0.020 0.035 G 1.27 BSC 0.050 BSC J J 0.25 0.32 0.010 0.012 K 0.10 0.25 0.004 0.009 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029 *MC88920/D* MC88920/D TIMING SOLUTIONS BR1333 — REV 5 NETCOM MC88920 ...
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... MPC92459 MC88920 PART NUMBERS 900 MHz Low Voltage LVDS Clock Synthesizer Low Skew CMOS PLL Clock Drivers With Power-Down/Power-up Feature INSERT PRODUCT NAME AND DOCUMENT TITLE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc ...