stcd1020 STMicroelectronics, stcd1020 Datasheet
stcd1020
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stcd1020 Summary of contents
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... Ultra-low phase noise and standby current ■ 2 3.6 V supply voltage ■ typical load driving capability ■ Available in TDFN packages – STCD1020 - 8-lead ( mm) – STCD1030 - 10-lead ( 2.5 mm) – STCD1040 - 12-lead ( mm) ■ Operational temperature : –40°C to 85°C Applications ■ ...
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Contents 1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Connections diagram (STCD1020, 2-channel Figure 3. Connections diagram (STCD1030, 3-channel Figure 4. Connections diagram (STCD1040, 4-channel Figure 5. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 6. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 7. Typical application circuit using STCD1040 for RF ends of TD-SCDMA/GSM dual mode mobile phone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 8. Typical application circuit using STCD1040 for baseband peripherals in mobile phone . . 12 Figure 9 ...
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Figure 30. STCD10x0 recovery time from standby to active (STCD1040, 1.8 V version, EN2=EN3=EN4=0, measure CLK1 when EN1 from ...
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... Device overview Figure 1. Logic diagram MCLK Note: No EN3, EN4, CLK3 nor CLK4 for STCD1020 and no EN4 nor CLK4 for STCD1030. Figure 2. Connections diagram (STCD1020, 2-channel) 6/ STCD1040 EN1 EN2 Clock distribution EN3 EN4 GND STCD1020 2 MCLK 3 TDFN8 EN1 4 EN2 CLK1 ...
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Figure 3. Connections diagram (STCD1030, 3-channel MCLK EN1 3 EN2 4 EN3 5 Figure 4. Connections diagram (STCD1040, 4-channel MCLK 3 EN1 4 EN2 5 EN3 6 EN4 GND ...
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Table 2. Pin names and functions Pin CLK1, CLK2, CLK3, CLK4 EN1, EN2, EN3, EN4 MCLK V CC GND NC Figure 5. Block diagram 8/40 Type Clock output channel #1, #2, #3, #4. A 0.001μ Output cut capacitor ...
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Figure 6. Hardware hookup Master Clock input V CC Clock enable control V CC EN4 Clock #4 CLK4 output STCD1040 EN3 Clock #3 MCLK CLK3 output EN2 Clock #2 CLK2 output EN1 Clock #1 CLK1 output GND ai13953 9/40 ...
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... The enable signals and output clock signals truth table are given in Table 3. The input DC cut capacitor is embedded in STCD1020, STCD1030 and STCD1040. A capacitor outside is needed for each of the clock outputs. The STCD1020, STCD1030 and STCD1040 are internally biased at 1/2 V Table 3. Truth table for enable signals (EN 1-4) and output clocks (CLK1-4) EN1 ...
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... The enable pins can also be connected to logic high to let the channel output always on. If the channels of STCD1020, STCD1030 and STCD1040 are not used in the application, the enable pins of the channels should be connected to ground on PCB. ...
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... VCTCXO 3.2 Connection of the source clock to MCLK If the output of the clock source voltage level is within the supply rails of the STCD1020, STCD1030 and STCD1040, the output of the source clock should be connected directly to the MCLK of the clock distribution circuits. This is described in connection of the source clock is the common case and a DC-CUT capacitor is saved on PCB ...
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... STCD1020, STCD1030 and STCD1040. The proper DC voltage is around half of the supply. The connection of the DC-CUT capacitor and bias for the STCD1020, STCD1030 and STCD1040 is only needed when the output of VCTCXO voltage level exceeds the supply of the clock distribution circuit (see Figure 10 ...
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... These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4. ...
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DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow are derived from tests performed under the measurement ...
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Table 7. DC and AC characteristics (1.8 V supply) Symbol Parameter (3)(8) P Additive phase noise N Buffer recovery time from off to t RECB on STCD10x0 active recovery time t RECC from standby to active C Capacitive load for ...
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Table 9. DC and AC characteristics (2.8 V supply) (continued) Symbol Parameter (5) I Active current ACT I Standby current SB R Input resistance IN C Input capacitance IN (6) t Rise/fall times r/f (3) BW Signal bandwidth (7) V ...
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Typical operating characteristics Typical operating characteristics of STCD1040 are V load capacitance = 10 pF, 26 MHz TCXO ENE3127B from NDK (except where noted). Figure 11. Quiescent current (I EN1=EN2=EN3=EN4=1, no master clock input) Figure 12. Quiescent current (I ...
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Figure 13. Standy current (I SB EN1=EN2=EN3=EN4=0, no master clock input) Standby current vs. Supply voltage 1 0.5 0 -0.5 -1 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Figure 14. Active current (I ...
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Figure 15. Active current (I (STCD1040, 2.8 V version, EN1=EN2=EN3=EN4=1, 26 MHz sine wave master clock input) Figure 16. Active current (I EN1=EN2=EN3=EN4=1, master clock input Vpp = 1 V) 20/40 ) vs. master clock input voltage level (Vpp) ACT ...
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Figure 17. STCD10x0 recovery time from standby to active (STCD1040, 2.8 V version, EN2=EN3=EN4=0, measure CLK1 when EN1 from Figure 18. STCD10x0 buffer recovery time from off to on (STCD1040, 2.8 V version, EN2=EN3=EN4=1, measure CLK1 when ...
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Figure 19. Sine wave input clock vs. output clock (STCD1040, 2.8 V version, 26 MHz sine wave master clock input from TCXO) Figure 20. Rise and fall time for square wave output (STCD1040, 2 MHz square wave master ...
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Figure 21. Input clock phase noise (STCD1040, 2.8 V version, 26 MHz master clock input from TCXO) Figure 22. Output clock phase noise (STCD1040, 2.8V version, this phase noise includes the additive phase noise from TCXO and STCD1040) 23/40 ...
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Figure 23. Clock bandwidth (STCD1040, 2.8 V version, C Figure 24. Quiescent current (I EN1=EN2=EN3=EN4=1, no master clock input) 24/40 Clock bandwidth 0.00 -1.00 -2.00 -3.00 -4.00 -5.00 -6.00 -7.00 -8. Input frequency (MHz) ) vs. supply voltage ...
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Figure 25. Quiescent current (I EN1=EN2=EN3=EN4=1, C Quiescent current vs. Temperature 2.9 2.7 2.5 2.3 2.1 1.9 1.7 1.5 -50 Figure 26. Standby current (I EN1=EN2=EN3=EN4=0, no master clock input) Standby current vs. Supply voltage 1 0.5 0 -0.5 -1 ...
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Figure 27. Active current (I EN1=EN2=EN3=EN4=1, 26 MHz sine wave master clock input from TCXO) Figure 28. Active current (I (STCD1040, 1.8 V version, EN1=EN2=EN3=EN4=1, 26 MHz sine wave master clock input) 26/40 ) vs. supply voltage (V ACT Active ...
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Figure 29. Active current (I ACT EN1=EN2=EN3=EN4=1, master clock input Vpp Figure 30. STCD10x0 recovery ...
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Figure 31. STCD10x0 buffer recovery time from off to on (STCD1040, 1.8 V version, EN2 =EN3=EN4=1, measure CLK1 when EN1 from Figure 32. Sine wave input clock vs. output clock (STCD1040, 1.8 V version, 26 MHz sine ...
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Figure 33. Rise and fall time for square wave output (STCD1040, 1.8 V version, 10MHz square wave master clock input, C Figure 34. Input clock phase noise (STCD1040, 1.8 V version, 26 MHz master clock input from TCXO ...
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Figure 35. Output clock phase noise (STCD1040, 1.8 V version, this phase noise includes the additive phase noise from TCXO and STCD1040) Figure 36. Clock bandwidth (STCD1040, 1.8 V version -0.5 -1 -1.5 -2 -2.5 -3 -3.5 0 ...
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Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner ...
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Figure 37. TDFN - 8-lead package outline PIN 1 INDEX AREA 0.10 C 0.08 C PIN 1 INDEX AREA 32/ TOP VIEW SIDE VIEW Pin ...
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Table 10. TDFN - 8-lead ( mm) package mechanical data mm Symbol Min. Typ. A 0.70 0.75 A1 0.00 0.02 b 0.15 0.20 2.00 D BSC 2.00 E BSC e 0.50 L 0.45 0.55 inches Max. Min. Typ. ...
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Figure 38. TDFN - 10-lead 2.5 mm package outline PIN 1 INDEX AREA 0.10 C 0.08 C PIN 1 INDEX AREA Pin#1 ID 34/ TOP VIEW SIDE VIEW e b 0.10 BOTTOM VIEW B ...
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Table 11. TDFN - 10-lead (2 x 2.5 mm) package mechanical data mm Symbol Min. Typ. A 0.70 0.75 A1 0.00 0.02 b 0.15 0.20 2.50 D BSC 2.00 E BSC e 0.50 L 0.45 0.55 inches Max. Min. Typ. ...
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Figure 39. TDFN - 12-lead package outline INDEX AREA (D/2xE/2) 0.10 C 0.08 C PIN#1 ID INDEX AREA (D/2xE/2) 36/40 D 0.10 C TOP VIEW SIDE VIEW BOTTOM VIEW B ...
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Table 12. TDFN - 12-lead ( mm) package mechanical data mm Symbol Min. Typ. A 0.70 0.75 A1 0.00 0.02 b 0.15 0.20 3.00 D BSC 2.00 E BSC e 0.50 L 0.45 0.55 inches Max. Min. Typ. ...
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Part numbering Table 13. Ordering information scheme Example: Device type STCD = clock distribution Channels 1020 = 2-channel 1030 = 3-channel 1040 = 4-channel Operating voltage R = 2.5 to 3 1.65 to 2.75 V ...
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Revision history Table 14. Document revision history Date Revision 08-Aug-2007 08-Oct-2007 03-Apr-2008 08-May-2008 1 Initial release. Addition of footnote 4 in Table 7: DC and AC characteristics (1 supply); updated Vout in Table 7 Updated cover page, ...
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... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...