nb4n441 ON Semiconductor, nb4n441 Datasheet
nb4n441
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nb4n441 Summary of contents
Page 1
... MHz. A Serial Peripheral Interface (SPI) is used to configure the device to produce one of sixteen popular standard protocol output frequencies from a single 27 MHz crystal reference. The NB4N441 also has the added feature of allowing application specific output frequencies from 12.5 MHz to 425 MHz using crystals within the range of 10 MHz to 28 MHz ...
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... SCLOCK Frequency Control Logic SLOAD GND 24 1 GND VCC_PLL GND 7 Figure 3. QFN−24 Lead Pinout (Top View) NB4N441 VCC_PLL Loop PFD VCO Filter OUTDIV (NB) B2 16, 32 Feedback Divider (MB) P[4:0] M[9:0] N[3:0] Serial Load Figure 2. Block Diagram Exposed Pad (EP ...
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... SCLOCK** 21 OE* 22, 23 CLKOUT CLKOUT EP *Pins will default HIGH when left Open **Pins will default LOW when left Open NB4N441 I/O Power Supply Positive supply voltage. PLL Power Supply Positive supply voltage for the PLL. Ground Ground. LVTTL Lock Output When Low, this output provides indication that the PLL is locked and the device is in proper operating mode ...
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... Table 3. N−DIVIDER TABLE NB4N441 Input Prescaler PLL FB Divider Divider P[4:0] CLKOUT (MHz) 155.52 11001 155.52 11001 155.52 11001 32 11011 51.84 11001 50 11011 50 11011 125 11011 125 11011 125 11011 125 11011 13.28125 11011 26 ...
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... Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. Maximum Ratings are those values beyond which device damage may occur. 3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). NB4N441 Characteristics Human Body Model Machine Model ...
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... Additive RMS jitter with 50% duty cycle input clock signal at 27.000 MHz 155 MHz. Protocol 13.28125 MHz will have typical period jitter (RMS and a typical cycle−to−cycle jitter of 95 ps. OUT NB4N441 = 3.135 V to 3.465 V, GND = −40°C to +85°C A ...
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... As the oscillator is somewhat sensitive to loading on its inputs, the user is advised to mount the crystal as close to the NB4N441 as possible to avoid any board level parasitic effects. To facilitate collocation, surface mount crystals are recommended, but not required. ...
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... Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The NB4N441 provides separate power supplies for the digital circuitry (V the internal PLL (PLL_V ) of the device ...
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... S_CLOCK S_DATA First S_LOAD S_DATA S_CLOCK S_DATA S_LOAD NB4N441 Bit Figure 5. Serial Interface Timing Diagram t HOLD t SETUP Figure 6. Setup and Hold t HOLD t SETUP Figure 7. Setup and Hold http://onsemi.com Bits Last Bit ...
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... The typical method of measuring jitter is to look at the timing signal with an oscilloscope and observe the variations in period−to−period NB4N441 or cycle−to−cycle. If the scope is set up to trigger on every rising or falling edge, set to infinite persistence mode and allowed to trace sufficient cycles possible to determine the maximum and minimum periods of the timing signal ...
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... Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device NB4N441MNG NB4N441MNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. NB4N441 = ...
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... Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com NB4N441 PACKAGE DIMENSIONS QFN 24 MN SUFFIX 24 PIN QFN, 4x4 CASE 485L− ...