adf4001 Analog Devices, Inc., adf4001 Datasheet
adf4001
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adf4001 Summary of contents
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... MHz Clock Generator PLL GENERAL DESCRIPTION The ADF4001 clock generator can be used to implement clock sources for PLLs that require very low noise, stable reference ) Allows Extended signals. It consists of a low noise digital PFD (phase frequency ...
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... IN 5 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value). 6 The phase noise is measured with the EVAL-ADF4001EB1 evaluation board and the HP8562E spectrum analyzer MHz 200 kHz; Offset Frequency = 1 kHz; f ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADF4001 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... can be set and used to drive a VCO or VCXO with a tuning DD range –4– LFCSP PIN 1 15 MUXOUT CPGND 1 INDICATOR 14 LE AGND 2 ADF4001 13 DATA AGND 3 12 CLK TOP VIEW pin is 0.66 V. The relationship ...
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... VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 SECONDS AVERAGES = 26 –40 –50 –60 –70 –80 –90 –100 –2kHz –1kHz 200MHz TPC 3. Phase Noise (200 MHz, 200 kHz, 20 kHz) REV. A Typical Performance Characteristics–ADF4001 10dB/DIVISION –40 –50 –60 –70 –80 – + –100 –110 –120 –130 T = – ...
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... CP OUTPUT Figure 5. PFD Simplified Schematic and Timing (In Lock) MUXOUT AND LOCK DETECT The output multiplexer on the ADF4001 family allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 in the function latch. Table V shows the full truth table. Figure 6 shows the MUXOUT section in block diagram form. – ...
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... When lock has been detected, this output will be high with narrow low-going pulses. INPUT SHIFT REGISTER The ADF4001 digital section includes a 24-bit input shift regis- ter, a 14-bit R counter, and a 13-bit N counter. Data is clocked CONTROL MUXOUT into the 24-bit shift register on each rising edge of CLK ...
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... ADF4001 ANTI- TEST BACKLASH RESERVED MODE WIDTH BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 LDP T2 T1 ABP2 X = DON’T CARE ABP2 TEST MODE BITS SHOULD BE SET TO 00 FOR NORMAL OPERATION LDP OPERATION 0 THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET ...
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... ADF4001 RESERVED DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DON’T CARE N COUNTER DIVIDE RATIO 8188 8189 8190 8191 ...
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... ADF4001 CURRENT CURRENT RESERVED SETTING SETTING 2 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 X X PD2 CPI6 CPI5 CPI4 CPI3 X = DON’T CARE TC4 TC3 CPI6 ...
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... ADF4001 MUXOUT CONTROL DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 PD1 F1 PHASE DETECTOR F2 POLARITY F1 0 NEGATIVE 0 ...
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... N counter resumes counting in close alignment with the R counter. (The maximum error is one prescaler cycle.) Power-Down DB3 (PD1) and DB21 (PD2) on the ADF4001 family provide programmable power-down modes. They are enabled by the CE pin. When the CE pin is low, the device is immediately disabled regardless of the states of PD2, PD1 ...
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... The charge pump output of the ADF4001 (Pin 2 of the TSSOP) drives the loop filter and the 13 MHz VCXO. The VCXO output is fed back to the RF input of the ADF4001 and also drives the reference (REF ) for the LO. A T-circuit configuration provides IN 50 Ω ...
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... A/D converter sample rate. Thus, when doing an FFT on this data, there is no longer any need to apply the window weighting function. Figure 8 shows how the ADF4001 can be used to handle all the possible combinations of the input signal frequency and sampling rate. The first ADF4001 is phase locked to a VCO. The output of the VCO is also fed into the N divider of the second ADF4001 ...
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... MicroConverter to the device. When the third byte has been written, the LE input should be brought high to complete the transfer. On first applying power to the ADF4001 family, it needs three writes (one each to the R counter latch, the N counter latch, and the initialization latch) for the output to become active. ...
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... ADF4001 16-Lead Thin Shrink Small Outline Package [TSSOP] 0.15 0.05 PIN 1 INDICATOR 12 MAX 1.00 0.90 0.80 SEATING PLANE Revision History Location 10/03—Data Sheet changed from REV REV. A. Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Changes to PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I ...