mc145425dw Freescale Semiconductor, Inc, mc145425dw Datasheet

mc145425dw

Manufacturer Part Number

mc145425dw

Description

Isdn Universal Digital Loop Transceivers

Manufacturer

Freescale Semiconductor, Inc

Datasheet

1.MC145425DW.pdf (16 pages)

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

ISDN Universal Digital Loop

Transceivers II

(UDLT II)

capable of providing 160 kbps full–duplex data communication over 26 AWG

and larger twisted–pair cable up to 1 km in length. These devices are primarily

used in digital subscriber voice and data telephone systems. In addition, the

devices meet and exceed the CCITT recommendations for data transfer rates

of ISDNs on a single twisted pair. The devices utilize a 512 kbaud MDPSK burst

modulation technique to supply the 160 kbps full–duplex data transfer rates.

The 160 kbps rate is provided through four channels. There are two B channels,

which are 64 kbps each. In addition, there are two D channels which are

16 kbps each.

with the existing MC145422 and MC145426 80 kbps UDLTs, as well as compa–

tibility with existing and evolving telephone switching hardware and software

architectures.

line card while the MC145425 (Slave) UDLT is designed for use at the remote

digital telset or data terminal.

REV 2 (Replaces ADI1251)

9/95

MOTOROLA

16 kbps D2

16 kbps D1

64 kbps B1

64 kbps B2

The MC145421 and MC145425 UDLTs are high–speed data transceivers

The MC145421 and MC145425 UDLTs are designed for upward compatibility

The MC145421 (Master) UDLT is designed for use at the telephone switch

Motorola, Inc. 1995

Employs CMOS Technology in Order to Take Advantage of Its Proven

Capability for Complex Analog and Digital LSI Functions

Provides Synchronous Full–Duplex 160 kbps Voice and Data

Communication in a 2B+2D Format for ISDN Compatibility

Provides the CCITT Basic Access Data Transfer Rate (2B+D) for ISDNs

on a Single Twisted Pair Up to 1 km

Compatible with Existing and Evolving Telephone Switch Architectures and

Call Signaling Schemes

Protocol Independent

Single + 5 V Power Supply

MC145421EVK is Available

ISDN UDLT

MASTER

160 kbps FULL–DUPLEX

DATA TRANSMISSION

TWISTED PAIR

WIRE

1 km

ISDN UDLT

SLAVE

16 kbps D1

16 kbps D2

64 kbps B1

64 kbps B2

MC145421P

MC145425P

MC145421DW SOG Package

MC145425DW SOG Package

ORDERING INFORMATION

MC145421

MC145425

MC145421 MC145425

PLASTIC PACKAGE

Plastic Package

Order this document

SOG PACKAGE

DW SUFFIX

CASE 751F

CASE 709

P SUFFIX

by MC145421/D

Related parts for mc145425dw

mc145425dw Summary of contents

Page 1

... SLAVE 16 kbps D2 ISDN UDLT 64 kbps B1 64 kbps B2 Order this document by MC145421/D MC145421 MC145425 P SUFFIX 24 PLASTIC PACKAGE 1 CASE 709 DW SUFFIX SOG PACKAGE 24 CASE 751F 1 ORDERING INFORMATION MC145421P Plastic Package MC145425P Plastic Package MC145421DW SOG Package MC145425DW SOG Package MC145421 MC145425 1 ...

Page 2

MC145421 — MASTER (PLASTIC AND SOG PACKAGES ref 2 23 LO1 LO2 RE2 D1I 6 19 RE1 D2I 7 18 TDC/RDC DCLK 8 ...

Page 3

MC145421 MASTER ISDN BLOCK DIAGRAM 23 + LO1 MODULATOR 22 – LO2 MSI 17 CCI ref DEMODULATOR MC145425 SLAVE ISDN BLOCK DIAGRAM 23 + LO1 ...

Page 4

ABSOLUTE MAXIMUM RATINGS (Voltage Referenced Rating DC Supply Voltage V DD – Voltage Any Pin Current, Any Pin (Excluding Operating Temperature Storage Temperature RECOMMENDED ...

Page 5

MC145421 MASTER PIN DESCRIPTIONS V DD Positive Supply (Pin 24) The most positive power supply pin, normally + 5 V with respect Negative Supply (Pin 1) The most negative supply pin and logic ground, ...

Page 6

DCLK D Channel Clock Input (Pin 8) This input is the transmit and receive data clock for both D channels. D channel input and output operation is de- scribed in the D1O, D2O pin description. Tx Transmit Data Output (Pin ...

Page 7

Mu/A Tone Format Input (Pin 11) This pin determines the PCM code for the 500 Hz square wave tone generated when the TONE input is high — Mu– Law (Mu CCITT A–Law (Mu format. TONE ...

Page 8

BACKGROUND The MC145421 and the MC145425 ISDN UDLTs provide an economical means of sending and receiving two B chan- nels (64 kbps each) of voice/data and two D channels (16 kbps each) of signal data in a two–wire configuration at ...

Page 9

In the master, time–out begins on the rising edge of the third MSI following the last received burst. This is equivalent to two MSI frames. The VD output is forced low during time– out. The B channel output data will ...

Page 10

EN1 EN2 DCLK 1 BCLK VD D1I, D2I D1O, D2O Tx B CHANNEL 1 OUTPUT Rx B CHANNEL 1 INPUT Figure 2. MC145425 Slave ISDN UDLT Timing Top Trace: MSI Bottom Trace: Outgoing burst measured at LI (with respect to ...

Page 11

LO1 LO2 MASTER OR SLAVE ISDN UDLT V ref LI TRANSFORMER PARAMETERS INDUCTANCE OF Tx: WINDING: 1.75 mH TURNS RATIO 2:1 TURNS RATIO 4:1 MOTOROLA + 5 V 110 110 Tx L1 ...

Page 12

SWITCHING CHARACTERISTICS ( Load = 50 pF) No.* Master Timing 1 TDC/RDC Pulse Width High 2 TDC/RDC Pulse Width Low 3 MSI Rising Edge to TDC/RDC Falling Edge ...

Page 13

MOTOROLA MC145421 MC145425 13 ...

Page 14

MC145421 MC145425 14 MOTOROLA ...

Page 15

- 28X 0.010 (0.25 -T- G 26X MOTOROLA PACKAGE DIMENSIONS P SUFFIX PLASTIC PACKAGE CASE 709– SEATING ...

Page 16

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of ...

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