hd74alvch162820 Renesas Electronics Corporation., hd74alvch162820 Datasheet

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hd74alvch162820

Manufacturer Part Number
hd74alvch162820
Description
3.3-v 10-bit Flip Flops With Dual Outputs And 3-state Outputs - Hitachi Semiconductor
Manufacturer
Renesas Electronics Corporation.
Datasheet
Description
The HD74ALVCH162820 flip flops are edge triggered D-type flip flops. On the positive transition of the
clock (CLK) input, the device provides true data at the Q outputs. A buffered output enable (OE) input can
be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high
impedance state. In the high impedance state, the outputs neither load nor drive the bus lines significantly.
The high impedance state and increased drive provide the capability to drive bus line without need for
interface or pullup components. OE does not affect the internal operations of the flip flops. Old data can
be retained or new data can be entered while the outputs are in the high impedance state. Active bus hold
circuitry is provided to hold unused or floating data inputs at a valid logic level. All outputs, which are
designed to sink up to 12 mA, include 26
Features
V
Typical V
Typical V
High output current 12 mA (@V
Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
All outputs have equivalent 26
3.3-V 10-bit Flip Flops with Dual Outputs and 3-state Outputs
CC
= 2.3 V to 3.6 V
OL
OH
ground bounce < 0.8 V (@V
undershoot > 2.0 V (@V
HD74ALVCH162820
series resistors, so no external resistors are required.
CC
= 3.0 V)
CC
= 3.3 V, Ta = 25 C)
resistors to reduce overshoot and undershoot.
CC
= 3.3 V, Ta = 25 C)
ADE-205-185B (Z)
December 1999
3rd. Edition

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hd74alvch162820 Summary of contents

Page 1

... Flip Flops with Dual Outputs and 3-state Outputs Description The HD74ALVCH162820 flip flops are edge triggered D-type flip flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs. A buffered output enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels high impedance state ...

Page 2

... HD74ALVCH162820 Function Table Inputs OEn *2 CLK High level L : Low level X : Immaterial Z : High impedance : Low to high transition Notes: 1. Output level before the indicated steady state input conditions were established Output ...

Page 3

... GND 11 4Q2 12 5Q1 13 5Q2 14 6Q1 15 6Q2 16 17 7Q1 GND 18 7Q2 19 8Q1 20 8Q2 9Q1 23 24 9Q2 GND 25 10Q1 26 10Q2 27 2OE 28 HD74ALVCH162820 CLK GND GND ...

Page 4

... HD74ALVCH162820 Absolute Maximum Ratings Item Symbol Supply voltage Input voltage V I *1, 2 Output voltage V O Input clamp current I IK Output clamp current I OK Continuous output current GND current / pin Maximum power dissipation (in still air) ...

Page 5

... Logic Diagram 1 1OE 28 2OE 56 CLK 55 D1 HD74ALVCH162820 nine other channels 1Q1 1Q2 5 ...

Page 6

... HD74ALVCH162820 Electrical Characteristics (Ta = – Item Symbol V CC Input voltage V 2.3 to 2.7 IH 2.7 to 3.6 V 2.3 to 2.7 IL 2.7 to 3.6 Output voltage V Min to Max V OH 2.3 2.3 3.0 2.7 3.0 V Min to Max — OL 2.3 2.3 3.0 2.7 3.0 Input current I 3 2.3 IN (hold) 2.3 3.0 3.0 3.6 *2 Off state output current I 3.6 OZ Quiescent supply current I 3 3.0 to 3.6 CC Notes: 1. For conditions shown as Min or Max, use the appropriate values under recommended operating conditions ...

Page 7

... HD74ALVCH162820 Unit FROM TO (Input) (Output) MHz ns CLK Control inputs Data inputs pF 7 ...

Page 8

... HD74ALVCH162820 • Test Circuit Note includes probe and jig capacitance. 8 500 500 L Load Circuit for Outputs Vcc=2.7V, Symbol Vcc=2.5 0.2V 3.3 0. PLH PHL OPEN OPEN GND GND 4 See under table OPEN ...

Page 9

... Waveforms – Input V ref PLH Output • Waveforms – 2 Timing Input V Data Input ref V Input ref HD74ALVCH162820 ref PHL V V ref ref ref ref ref V IH GND GND ...

Page 10

... HD74ALVCH162820 • Waveforms – Output V ref Control 10 % Waveform - A Waveform - B Notes: 1. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz Waveform – for an output with internal conditions such that the output is low except when disabled by the output control. ...

Page 11

... Package Dimensions +0.3 14.00 –0 0.50 +0.1 0.08 0.20 –0.05 0.40 Max 0. 8.10 0.3 Hitachi code EIAJ code JEDEC code HD74ALVCH162820 Unit : mm 10 Max 0.50 0.1 TTP-56D — — 11 ...

Page 12

... HD74ALVCH162820 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document ...

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