hd74cdc2510b Renesas Electronics Corporation., hd74cdc2510b Datasheet

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hd74cdc2510b

Manufacturer Part Number
hd74cdc2510b
Description
3.3-v Phase-lock Loop Clock Driver - Hitachi Semiconductor
Manufacturer
Renesas Electronics Corporation.
Datasheet

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Description
The HD74CDC2510B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a
phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the
clock (CLK) input signal.
HD74CDC2510B operates at 3.3 V V
Bank of outputs provide ten low-skew, low-jitter copies of the input clock. Output signal duty cycles are
adjusted to 50 percent independent of the duty cycle at the input clock. Bank of outputs can be enabled or
disabled via the control (G) inputs. When the G inputs are high, the outputs switch in phase and frequency
with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the HD74CDC2510B does not require external RC networks. The
loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, HD74CDC2510B requires a stabilization time to achieve phase lock
of the feedback signal to the reference signal. This stabilization time is required, following power up and
application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL
reference or feedback signals. The PLL can be bypassed for test purposes by strapping AV
Features
Note: Only by a change of a suffix (A to B) for standardization, there isn’t any change of the product.
Meets “PC SDRAM registered DIMM design support document, Rev. 1.2”
Phase-lock loop clock distribution for synchronous DRAM applications
External feedback (FBIN) pin is used to synchronize the outputs to the clock input
No external RC network required
Support spread spectrum clock (SSC) synthesizers
3.3-V Phase-lock Loop Clock Driver
HD74CDC2510B
It is specifically designed for use with synchronous DRAMs.
CC
and is designed to drive up to five clock loads per output.
ADE-205-219F (Z)
CC
October 1999
to ground.
7th. Edition
The

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hd74cdc2510b Summary of contents

Page 1

... Unlike many products containing PLLs, the HD74CDC2510B does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, HD74CDC2510B requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals ...

Page 2

... HD74CDC2510B Function Table CLK High level L : Low level X : Immaterial Pin Arrangement AGND V CC 1Y0 1Y1 1Y2 GND GND 1Y3 1Y4 FBOUT (0: ...

Page 3

... CC GND P 0 –65 to +150 C stg 3.0 — 3.6 2.0 — — — — 0.8 0 — — — –12 — — — 85 HD74CDC2510B Conditions V < < > Unit Conditions ...

Page 4

... HD74CDC2510B Logic Diagram CLK 13 FBIN PLL 3 1Y0 4 1Y1 5 1Y2 8 1Y3 9 1Y4 15 1Y5 16 1Y6 17 1Y7 20 1Y8 21 1Y9 12 FBOUT ...

Page 5

... Ground Ground Description Clock input. CLK provides the clock signal to be distributed by the HD74CDC2510B clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal ...

Page 6

... HD74CDC2510B Electrical Characteristics Symbol Min Input clamp voltage V — IK Output voltage V V –0 2.1 2.4 V — OL — — Input current I — IN Quiescent supply I — current I — Input capacitance C — IN Output capacitance C — O Note: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions ...

Page 7

... P– Unit 50 125 MHz — HD74CDC2510B From (Input) To (Output) 66 MHz < FBIN CLKIN 100 MHz Any Y or FBOUT Any Y or FBOUT F (clkin = Any Y or 100 MHz) FBOUT F (clkin = Any 100 MHz) FBOUT Any Y or ...

Page 8

... HD74CDC2510B Test Circuit From output under test Note includes probe and jig capacitance. L Waveforms – 1 Input 50% V Output 50% V (=FBOUT) Notes: 1. All input pulses are supplied by generators having the following characteristics: PRR MHz 1.2 ns The outputs are measured one at a time with one transition per measurement. ...

Page 9

... Waveforms – 2 CLKIN t phase error FBIN FBOUT t sk (o) Any Y Any (o) Any Y HD74CDC2510B 9 ...

Page 10

... HD74CDC2510B Package Dimensions 7.80 8.10 Max 0.65 +0.08 0.22 –0.07 0.13 M 0.20 0.06 0.65 Max 0.10 Dimension including the plating thickness Base material dimension 10 1.0 6.4 0.2 0 – 8 0.5 0.1 Hitachi Code TTP-24DB JEDEC — EIAJ — Weight (reference value) 0.08 g Unit : mm ...

Page 11

... Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 HD74CDC2510B Hitachi Asia Pte. Ltd. Hitachi Asia (Hong Kong) Ltd. 16 Collyer Quay #20-00 Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Hitachi Tower ...

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