sy604 Micrel Semiconductor, sy604 Datasheet

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sy604

Manufacturer Part Number
sy604
Description
Sy604 125 Mhz Trigger Programmable Timing Edge Vernier
Manufacturer
Micrel Semiconductor
Datasheet

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FEATURES
D0 - D7
BLOCK DIAGRAM
True 125MHz retrigger rate
Pin-compatible with Bt604
15ps delay resolution
Less than
Differential TRIGGER inputs
Delay spans from 4 to 40ns
Compatible with 10KH ECL logic
Lower power dissipation 350mW typical
Available in 28-pin plastic (PLCC) or metal (MLCC)
J-lead package
V
TRIG
BB
CE
8
1 LSB timing accuracy
D
LATCH
FF
R
0 = STOP
1 = RUN
8
+
DAC
GENERATOR
LINEAR
IEXT
RAMP
PULSE
GEN
I/V
125MHz TRIGGER
PROGRAMMABLE TIMING
EDGE VERNIER
OUT
1
(delay generator) whose time delay is programmed via an 8-
bit code which is loaded concurrently with the circuit trigger.
The SY604 is fabricated in Micrel-Synergy's proprietary
ASSET™ bipolar process.
with a delay span as short as 4ns. At minimum span, the
resolution is 4ns/255 = 15.7ps per step. The delay span is
externally adjustable up to 40ns. The SY604 employs
differential TRIGGER inputs, and produces a differential
OUTPUT pulse; all other control signals are single-ended
ECL. Edge delay is specified by an 8-bit input which is loaded
into the device with the TRIGGER. The output pulse width will
typically be 3.5ns.
to provide precise timing edge placement; it is also found in
many instrumentation and communications applications.
ASSET™ technology result in not only ultra-fast performance,
but allow device operation at lower power dissipation than
competing technologies. Outstanding reliability is achieved in
volume production.
DESCRIPTION
PIN CONFIGURATION
Micrel-Synergy's SY604 is an ECL-compatible timing vernier
This device can be retriggered at speeds up to 125MHz,
The SY604 is commonly used in Automatic Test Equipment
Micrel-Synergy's circuit design techniques coupled with
D
D
D
D
D
D
D
0
1
2
3
4
5
6
26
27
28
2
1
3
4
25 24 23
5
6
TOP VIEW
7
PLCC
J28-1
22
8
21 20 19
9 10 11
18
17
16
15
14
13
12
Rev.: E
Issue Date: May, 1998
IEXT
NC
COMP
CE
COMP
NC
V
BB
Amendment: /0
SY604
FINAL
2
1

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sy604 Summary of contents

Page 1

... ECL. Edge delay is specified by an 8-bit input which is loaded into the device with the TRIGGER. The output pulse width will typically be 3.5ns. The SY604 is commonly used in Automatic Test Equipment to provide precise timing edge placement also found in many instrumentation and communications applications. ...

Page 2

... When the ramp level reaches that of the DAC, the comparator initiates the pulse generator to produce an output pulse of fixed width. The generation of an output pulse resets the ramp and the cycle is ready to begin again. DATA Figure 1. 2 SY604 , and COMP2 and V EE0 EE0 ...

Page 3

... SY604 Unit ˚C V Max. Unit -735 mV -1450 mV -735 mV -1600 mV 150 A 150 A 150 A 150 A 0.9 LSB 1.0 -1.25 V 2.80 mA 2.40 mA 1.20 mA 0.80 mA 0.60 mA 0.40 mA 6.5 ns 3.8 ns 4.9 ns 6.0 ns 7.1 ns 8.2 ns 9.3 ns 100 mA ...

Page 4

... Periods (ns) 8.0 10.0 11.1 12.5 14.3 16.6 20.0 25.0 33.3 SY604 Max. Unit — 125 MHz 1.0 — ns 3.5 4.5 ns 750 ps — — ns 220 ps/ns ns — — 157 ps 2 — ps/˚C 2 — ps/˚C 60 — ps/V — — ...

Page 5

... Micrel TIMING DIAGRAMS TRIG OUT DATA t DELAY ± 1 LSB Span vs. Trigger Rates 9 INL - 0.92LSB 8 7 INL - 0.86LSB 6 INL - 0.9LSB 100 110 120 130 Frequency (MHz) Figure 2. 5 SY604 INL - 1.14LSB ...

Page 6

... F ceramic capacitor REXT 1% metal film resistor (selected for proper Tspan) NOTE: The vendor numbers above are listed only as a guide. Substitution of devices with similar characteristics will not affect the performance of the SY604. All devices should be as close as possible to the SY604. V EE1 V ...

Page 7

... Micrel 7 SY604 ...

Page 8

... This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc (408) 914-7878 http://www.micrel.com FAX WEB © 2000 Micrel Incorporated 8 SY604 Rev. 03 ...

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