74lvc1g57gw NXP Semiconductors, 74lvc1g57gw Datasheet

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74lvc1g57gw

Manufacturer Part Number
74lvc1g57gw
Description
Low-power Configurable Multiple Function Gate
Manufacturer
NXP Semiconductors
Datasheet

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Part Number:
74LVC1G57GW
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Part Number:
74lvc1g57gw,125
Manufacturer:
NXP Semiconductors
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74lvc1g57gwЈ¬125
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NXP
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1. General description
2. Features
The 74LVC1G57 provides configurable multiple functions. The output state is determined
by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
NOR, XNOR, inverter and buffer. All inputs can be connected to V
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
The I
the device when it is powered down.
All inputs (A, B and C) have Schmitt trigger action. They are capable of transforming
slowly changing input signals into sharply defined, jitter-free output signals.
74LVC1G57
Low-power configurable multiple function gate
Rev. 03 — 19 July 2007
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
ESD protection:
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
24 mA output drive (V
OFF
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
circuitry disables the output, preventing the damaging backflow current through
CC
= 3.0 V)
CC
Product data sheet
or GND.
OFF
.

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74lvc1g57gw Summary of contents

Page 1

Low-power configurable multiple function gate Rev. 03 — 19 July 2007 1. General description The 74LVC1G57 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, ...

Page 2

... C to +125 C 74LVC1G57GV +125 C 74LVC1G57GM +125 C 74LVC1G57GF +125 C 4. Marking Table 2. Marking Type number 74LVC1G57GW 74LVC1G57GV 74LVC1G57GM 74LVC1G57GF 5. Functional diagram Fig 1. Logic symbol 74LVC1G57_3 Product data sheet Low-power configurable multiple function gate Name Description SC-88 plastic surface-mounted package; 6 leads SC-74 plastic surface-mounted package (TSOP6) ...

Page 3

... NXP Semiconductors 6. Pinning information 6.1 Pinning 74LVC1G57 GND 001aaf138 Fig 2. Pin configuration SOT363 (SC-88) and SOT457 (SC-74) 6.2 Pin description Table 3. Pin description Symbol Pin B 1 GND Functional description [1] Table 4. Function table Input ...

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... NXP Semiconductors 7.1 Logic configurations Table 5. Function selection table Logic function 2-input AND 2-input AND with both inputs inverted 2-input NAND with inverted input 2-input OR with inverted input 2-input NOR 2-input NOR with both inputs inverted 2-input XNOR Inverter Buffer ...

Page 5

... NXP Semiconductors Fig 11. Buffer 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK V input voltage I I output clamping current OK V output voltage ...

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... NXP Semiconductors 10. Static characteristics Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V LOW-level output voltage I = 100 HIGH-level ...

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... NXP Semiconductors 11. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for load circuit see Symbol Parameter Conditions t propagation delay see power dissipation capacitance [1] Typical values are measured at nominal V [ the same as t ...

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... NXP Semiconductors Table 10. Measurement points Supply voltage Input 1. 1.95 V 0.5V 2 2.7 V 0.5V 2.7 V 1 3.6 V 1 5.5 V 0.5V Measurement points are given in Definitions test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance Z ...

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... NXP Semiconductors 13. Transfer characteristics Table 12. Transfer characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V positive-going see T+ threshold voltage Figure negative-going see T threshold voltage Figure hysteresis voltage see Figure 16 T+ ...

Page 10

... NXP Semiconductors Fig 16. Transfer characteristic Fig 18. Typical 74LVC1G57 transfer characteristic; V 74LVC1G57_3 Product data sheet mnb154 Fig 17. Definition (mA 3 Rev. 03 — 19 July 2007 74LVC1G57 Low-power configurable multiple function gate V T+ ...

Page 11

... NXP Semiconductors 15. Package outline Plastic surface-mounted package; 6 leads y 6 pin 1 index DIMENSIONS (mm are the original dimensions UNIT max 0.30 1.1 0.25 mm 0.1 0.20 0.8 0.10 OUTLINE VERSION IEC SOT363 Fig 19. Package outline SOT363 (SC-88) 74LVC1G57_3 Product data sheet scale ...

Page 12

... NXP Semiconductors Plastic surface-mounted package (TSOP6); 6 leads y 6 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT b p 0.1 0.40 1.1 0.26 mm 0.013 0.25 0.9 0.10 OUTLINE VERSION IEC SOT457 Fig 20. Package outline SOT457 (SC-74) 74LVC1G57_3 Product data sheet scale ...

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... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1. (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 1.5 mm 0.5 0.04 0.17 1.4 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION ...

Page 14

... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 0 (1) terminal 1 index area DIMENSIONS (mm are the original dimensions UNIT b D max max 0.20 1.05 mm 0.5 0.04 0.12 0.95 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION IEC SOT891 Fig 22. Package outline SOT891 (XSON6) ...

Page 15

... Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section 10 “Static Changed: Conditions for input leakage current and supply current. ...

Page 16

... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...

Page 17

... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 7.1 Logic configurations . . . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 12 Waveforms ...

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