adc1173cimtcx National Semiconductor Corporation, adc1173cimtcx Datasheet - Page 14

• Manufacturer Part Number: adc1173cimtcx
• Description: 8-bit, 3-volt, 15msps, 33mw A/d Converter
• Manufacturer: National Semiconductor Corporation

www.national.com
Functional Description
The ADC1173 uses a new, unique architecture to achieve 7.4
effective bits at and maintains superior dynamic performance
up to ½ the clock frequency.
The analog signal at V
by V
Input voltages below V
of all zeroes. Input voltages above V
word to consist of all ones. V
analog supply voltage, AV
2.0 Volts. V
than V
If V
connected together, the nominal values of V
1.56V and 0.36V, respectively. If V
together and V
1.38V.
Data is acquired at the falling edge of the clock and the digital
equivalent of the data is available at the digital outputs the
pipeline delay (2.5 clock cycles) plus t
will convert as long as the clock signal is present at pin 12.
The Output Enable pin OE, when low, enables the output pins.
The digital outputs are in the high impedance state when the
OE pin is high.
Applications Information
1.0 THE ANALOG INPUT
The analog input of the ADC1173 is a switch followed by an
integrator. The input capacitance changes with the clock lev-
el, appearing as 4 pF when the clock is low, and 11 pF when
the clock is high. Since a dynamic capacitance is more difficult
to drive than a fixed capacitance, choose an amplifier that can
drive this type of load. The LMH6702, LMH6609, LM6152,
LM6154, LM6181 and LM6182 have been found to be excel-
lent devices for driving the ADC1173. Do not drive the input
beyond the supply rails.
RT
RT
and V
RB
and V
.
RT
RTS
RB
should always be at least 1.0 Volt more positive
RB
are connected together and V
are digitized to eight bits at up to 20 MSPS.
is grounded, the nominal value of V
RB
IN
will cause the output word to consist
that is within the voltage range set
DD
RT
, while V
has a range of 1.0 Volt to the
RT
and V
RT
OD
RB
will cause the output
later. The ADC1173
has a range of 0 to
RTS
RB
RT
are connected
and V
and V
RBS
RB
RT
are
are
is
14
Figure 3 shows an example of an input circuit using the
LM6181. This circuit has both gain and offset adjustments. If
you desire to eliminate these adjustments, you should reduce
the signal swing to avoid clipping at the ADC1173 output that
can result from normal tolerances of all system components.
With no adjustments, the nominal value for the amplifier feed-
back resistor is 510Ω and the 5.1k resistor at the inverting
input should be changed to 860Ω and returned to +3V rather
than to the Offset Adjust potentiometer.
Driving the analog input with input signals up to 2.8V
result in normal behavior where voltages above V
in a code of FFh and input voltages below V
output code of zero. Input signals above 2.8V
in odd behavior where the output code is not FFh when the
input exceeds V
2.0 REFERENCE INPUTS
The reference inputs V
ence Bottom) are the top and bottom of the reference ladder.
Input signals between these two voltages will be digitized to
8 bits. External voltages applied to the reference input pins
should be within the range specified in the Operating Ratings
table (1.0V to AV
Any device used to drive the reference pins should be able to
source sufficient current into the V
current from the V
The reference ladder can be self-biased by connecting V
V
reference voltages of approximately 1.56V and 0.36V, re-
spectively, with V
Figure 3. If V
analog ground, a top reference voltage of approximately
1.38V is generated. The top and bottom of the ladder should
be bypassed with 10µF tantalum capacitors located close to
the reference pins.
RTS
and connecting V
RT
and V
RT
DD
RB
.
CC
for V
pin.
= 3.0V. This connection is shown in
RTS
RB
RT
RT
are tied together, but V
to V
(Reference Top) and V
and 0V to (AV
RBS
to provide top and bottom
RT
pin and sink sufficient
DD
RB
- 1.0V) for V
will result in an
P-P
RT
RB
may result
RB
will result
is tied to
(Refer-
P-P
RT
RB
will
to
).