adc1173cimtcx National Semiconductor Corporation, adc1173cimtcx Datasheet - Page 18

• Manufacturer Part Number: adc1173cimtcx
• Description: 8-bit, 3-volt, 15msps, 33mw A/d Converter
• Manufacturer: National Semiconductor Corporation

www.national.com
Be especially careful with the layout of inductors. Mutual in-
ductance can change the characteristics of the circuit in which
they are used. Inductors should not be placed side by side,
not even with just a small part of their bodies being beside
each other.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any ex-
ternal component (e.g., a filter capacitor) connected between
the converter's input and ground should be connected to a
very clean point in the analog ground return.
6.0 DYNAMIC PERFORMANCE
The ADC1173 is AC tested and its dynamic performance is
guaranteed. To meet the published specifications, the clock
source driving the CLK input must be free of jitter. For best
a.c. performance, isolating the ADC clock from any digital cir-
cuitry should be done with adequate buffers, as with a clock
tree. See Figure 6.
FIGURE 6. Isolating the ADC clock from Digital Circuitry.
It is good practice to keep the ADC clock line as short as pos-
sible and to keep it well away from any other signals. Other
signals can introduce jitter into the clock signal.
7.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 50mV below the ground pins or 50mV above the
supply pins. Exceeding these limits on even a transient basis
can cause faulty or erratic operation. It is not uncommon for
high speed digital circuits (e.g., 74F and 74AC devices) to
exhibit undershoot that goes more than a volt below ground.
A resistor of 50Ω in series with the offending digital input will
usually eliminate the problem.
Care should be taken not to overdrive the inputs of the
ADC1173. Such practice may lead to conversion inaccura-
cies and even to device damage.
FIGURE 7. 5.5 MHz Low Pass Filter to Eliminate Harmonics at the Signal Input.
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Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current is re-
quired from DV
spikes can couple into the analog section, degrading dynamic
performance. Buffering the digital data outputs (with an
74ACQ541, for example) may be necessary if the data bus to
be driven is heavily loaded. Dynamic performance can also
be improved by adding 47Ω to 100Ω series resistors at each
digital output, reducing the energy coupled back into the con-
verter output pins.
Using an inadequate amplifier to drive the analog input.
As explained in Section 1.0, the capacitance seen at the input
alternates between 4 pF and 11 pF with the clock. This dy-
namic capacitance is more difficult to drive than is a fixed
capacitance, and should be considered when choosing a
driving device. The LMH6702, LM6152, LM6154, LM6181
and LM6182 have been found to be excellent devices for
driving the ADC1173 analog input.
Driving the V
not source or sink the current required by the ladder. As
mentioned in section 2.0, care should be taken to see that any
driving devices can source sufficient current into the V
and sink sufficient current from the V
not driven with devices than can handle the required current,
these reference pins will not be stable, resulting in a reduction
of dynamic performance.
Using a clock source with excessive jitter, using an ex-
cessively long clock signal trace, or having other signals
coupled to the clock signal trace. This will cause the sam-
pling interval to vary, causing excessive output noise and a
reduction in SNR performance. Simple gates with RC timing
is generally inadequate as a clock source.
Input test signal contains harmonic distortion that inter-
feres with the measurement of dynamic signal to noise
ratio. Harmonic and other interfering signals can be removed
by inserting a filter at the signal input. Suitable filters are
shown in Figure 7 and Figure 8. The circuit of Figure 7 has
cutoff of about 5.5 MHz and is suitable for input frequencies
of 1 MHz to 5 MHz. The circuit of Figure 8 has a cutoff of about
11 MHz and is suitable for input frequencies of 5 MHz to 10
MHz. These filters should be driven by a generator of 75 Ohm
source impedance and terminated with a 75 ohm resistor.
RT
DD
10089018
pin or the V
and DGND. These large charging current
RB
pin with devices that can
RB
pin. If these pins are
RT
pin