uda1334ats NXP Semiconductors, uda1334ats Datasheet
uda1334ats
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uda1334ats Summary of contents
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... DATA SHEET UDA1334ATS Low power audio DAC with PLL Product specification Supersedes data of 2000 Feb 09 File under Integrated Circuits, IC01 INTEGRATED CIRCUITS 2000 Jul 31 ...
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... DC CHARACTERISTICS 14 AC CHARACTERISTICS 14.1 Analog 14.2 Timing 15 APPLICATION INFORMATION 16 PACKAGE OUTLINE 17 SOLDERING 17.1 Introduction to soldering surface mount packages 17.2 Reflow soldering 17.3 Wave soldering 17.4 Manual soldering 17.5 Suitability of surface mount IC packages for wave and reflow soldering methods 18 DATA SHEET STATUS 19 DEFINITIONS 20 DISCLAIMERS 2 Product specification UDA1334ATS ...
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... GENERAL DESCRIPTION The UDA1334ATS is a single chip 2 channel digital-to-analog converter employing bitstream conversion techniques, including an on-board PLL. The extremely low power consumption and low voltage requirements make the device eminently suitable for use in low-voltage low-power portable digital audio equipment which incorporates a playback function ...
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... A-weighted kHz kHz dB; s A-weighted f = 44.1 kHz; code = 0; s A-weighted kHz; code = 0; s A-weighted audio mode video mode 4 Product specification UDA1334ATS MIN. TYP. MAX. UNIT 2.4 3.0 3.6 V 2.4 3.0 3.6 V 3.5 mA 3.5 mA 2 +85 C 900 ...
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... BCK DATAI UDA1334ATS 6 SYSCLK/PLL1 8 MUTE 9 DEEM/CLKOUT 14 VOUTL 2000 Jul 31 V DDD 4 DIGITAL INTERFACE DE-EMPHASIS INTERPOLATION FILTER NOISE SHAPER DAC DDA V SSA Fig.1 Block diagram. 5 Product specification UDA1334ATS V SSD PLL0 10 5 PLL 7 SFOR1 11 SFOR0 DAC 16 VOUTR 12 MGL973 V ref(DAC) ...
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... PLL0 MUTE 8 9 DEEM/CLKOUT MGL972 Fig.2 Pin configuration. 6 Product specification UDA1334ATS DESCRIPTION bit clock input word select input serial data input digital supply voltage digital ground system clock input in video mode/PLL mode control 1 input in audio mode serial format select 1 input ...
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... In video mode, the digital audio input is slave, which means that the system must generate the BCK and WS signals from the output clock available at pin CLKOUT of the UDA1334ATS. The digital audio signals should be frequency locked to the CLKOUT signal. Remarks: 1. The WS edge MUST fall on the negative edge of the ...
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... UDA1334ATS Fig.3 Power-on reset circuit. 2000 Jul 31 8.5 The UDA1334ATS has an internal Power-on reset circuit (see Fig.3) which resets the test control block. The reset time (see Fig.4) is determined by an external capacitor which is connected between pin V ground. The reset time should be at least 1 s for ...
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... DEEM/CLKOUT can be used to activate the digital de-emphasis for 44.1 kHz as given in Table 5. Table 5 De-emphasis control (audio mode) 8.6.3 The output signal can be soft muted by setting pin MUTE INPUT FORMAT to HIGH as given in Table 6. Table 6 Mute control 9 Product specification UDA1334ATS EMPHASIS CONTROL DEEM/CLKOUT FUNCTION LOW de-emphasis off HIGH ...
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Acrobat reader. white to force landscape pages to be ... LEFT BCK DATA MSB B2 MSB ...
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... V. DAC operation after short-circuiting cannot be warranted. DDA PARAMETER = all voltages with respect to ground (pins V L CONDITIONS note 1 note 1 audio mode video mode audio mode video mode 11 Product specification UDA1334ATS MIN. MAX. 4.0 150 65 +125 40 +85 2000 +2000 250 +250 450 ...
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... V amb L CONDITIONS (FS) digital input; note 44.1 kHz 44.1 kHz dB; A-weighted kHz kHz dB; A-weighted s 12 Product specification UDA1334ATS MIN. TYP. MAX. 2.0 5.0 0 0.5 DDD DDD 0.4V 0.6V DDD DDD ...
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... V L CONDITIONS f = 12.228 MHz 18.432 MHz 12.228 MHz 18.432 MHz 12.228 MHz 18.432 MHz o 13 Product specification UDA1334ATS TYP. 100 98 100 = 30 mV (p-p) 60 MIN. TYP. MAX. 81.38 54.25 0.3T 0.7T sys sys 0.4T 0.6T sys sys 0.3T 0.7T sys sys 0 ...
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... Low power audio DAC with PLL t CWH handbook, full pagewidth handbook, full pagewidth WS t BCKH t r BCK T cy(BCK) DATAI 2000 Jul 31 t CWL T sys Fig.6 Output clock timing. t h(WS) t su(WS BCKL Fig.7 Serial interface timing. 14 Product specification UDA1334ATS MGR984 t su(DATAI) t h(DATAI) MGL880 ...
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... V) ( SSA V DDA V SSD V DDD UDA1334ATS Fig.8 Audio mode application diagram. 15 Product specification UDA1334ATS VOUTL 14 100 ( 220 k ( VOUTR 16 100 ...
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... PLL0 In video mode, a clock output signal is generated by the UDA1334ATS which is master for the audio signals in the system; the digital audio interface is slave, which means the system must generate the BCK and WS signal from the UDA1334ATS output clock. 2000 Jul 31 ...
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... VERSION IEC SOT369-1 2000 Jul 2.5 scale (1) ( 0.32 0.25 5.30 4.5 6.6 0.65 0.20 0.13 5.10 4.3 6.2 REFERENCES JEDEC EIAJ MO-152 17 UDA1334ATS detail 0.75 0.65 1.0 0.2 0.13 0.45 0.45 EUROPEAN PROJECTION Product specification SOT369 ( 0. ...
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... Use a low voltage ( less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 18 Product specification UDA1334ATS ...
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... Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2000 Jul 31 SOLDERING METHOD WAVE not suitable (2) not suitable suitable (3)(4) not recommended (5) not recommended 19 Product specification UDA1334ATS (1) REFLOW suitable suitable suitable suitable suitable ...
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... Product specification UDA1334ATS (1) These products are not Philips Semiconductors ...
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... Philips Semiconductors Low power audio DAC with PLL 2000 Jul 31 NOTES 21 Product specification UDA1334ATS ...
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... Philips Semiconductors Low power audio DAC with PLL 2000 Jul 31 NOTES 22 Product specification UDA1334ATS ...
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... Philips Semiconductors Low power audio DAC with PLL 2000 Jul 31 NOTES 23 Product specification UDA1334ATS ...
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Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. + 101 ...