uda1321 NXP Semiconductors, uda1321 Datasheet

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uda1321

Manufacturer Part Number
uda1321
Description
Universal Serial Bus Usb Digital-to-analog Converter Dac
Manufacturer
NXP Semiconductors
Datasheet

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Preliminary specification
Supersedes data of 1998 May 12
File under Integrated Circuits, IC01
DATA SHEET
UDA1321
Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)
INTEGRATED CIRCUITS
1998 Oct 06

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uda1321 Summary of contents

Page 1

... DATA SHEET UDA1321 Universal Serial Bus (USB) Digital-to-Analog Converter (DAC) Preliminary specification Supersedes data of 1998 May 12 File under Integrated Circuits, IC01 INTEGRATED CIRCUITS 1998 Oct 06 ...

Page 2

... USB headsets USB telephone/answering machines USB links in consumer audio devices. GENERAL DESCRIPTION The UDA1321 is a stereo CMOS digital-to-analog bitstream converter designed for USB-compliant audio playback devices and multimedia audio applications.The UDA1321 is an adaptive asynchronous sink USB audio device with a continuous sampling frequency (f ) range from kHz ...

Page 3

... The audio information from the USB interface is fed directly to the ADAC. 3. The power-save mode (power management) is not supported in the UDA1321/N101; see Chapter “USB-DAC UDA1321/N101 (Firmware sw 2.1.1.7)”. 1998 Oct 06 The ADAC consists of FIFO registers, a unique audio ...

Page 4

... QFP64 UDA1321T/N101 SO28 UDA1321PS/N101 SDIP32 1998 Oct 06 PACKAGE DESCRIPTION plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 20 2.8 mm plastic small outline package; 28 leads; body width 7.5 mm plastic shrink dual in-line package; 32 leads (400 mil) 4 Preliminary specification UDA1321 VERSION SOT319-2 SOT136-1 SOT232-1 ...

Page 5

... VARIABLE HOLD REGISTER 128f s TIMING 3rd-ORDER NOISE SHAPER LEFT RIGHT DAC DAC REFERENCE VOLTAGE V ref Fig.1 Block diagram. 5 Preliminary specification UDA1321 SCL SDA EA PSEN ALE P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 MICRO- CONTROLLER P2.6 P2.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 V DDE V SSE V SSI UDA1321H V DDI UDA1321T UDA1321PS V DDO V SSO V DDA V SSA VOUTR MGM839 ...

Page 6

... O crystal oscillator output crystal oscillator supply voltage reference output voltage 19 16 analog ground 20 17 analog supply voltage right channel output voltage 22 19 operational amplifier ground 6 Preliminary specification UDA1321 DESCRIPTION 2 C-bus) 2 C-bus) ...

Page 7

... Port 0.2 of the microcontroller n.a. I/O Port 0.3 of the microcontroller n.a. I/O Port 0.4 of the microcontroller asynchronous reset input for test control box (active HIGH) n.a. I/O Port 0.5 of the microcontroller n.a. I/O Port 0.6 of the microcontroller 27 24 I/O general purpose pin 0 or master bit clock input n.a. not connected 28 7 Preliminary specification UDA1321 DESCRIPTION ...

Page 8

... EA GP1/DI 7 PSEN 8 ALE 9 GP2/DO 10 P2.0 11 P2.1 12 GP3/WSO 13 GP4/BCKO 14 SHTCB 15 n. P2.2 18 P2.3 19 1998 Oct 06 UDA1321H Fig.2 Pin configuration QFP64. 8 Preliminary specification UDA1321 V DDO 51 n. SSO 49 n. VOUTR V DDA 45 V SSA 44 n. REF 42 n. DDX 39 38 XTAL2 37 XTAL1 V SSX ...

Page 9

... GP1/ GP3/WSO 2 31 SDA GP4/BCKO 3 30 SCL SHTCB 4 29 GP5/WSI n. n. GP0/BCKI RTCB V DDI UDA1321PS V SSI VOUTL DDO V SSE SSO V DDE 11 22 VOUTR n. DDA V SSX SSA 14 19 XTAL1 V ref 15 18 XTAL2 V DDX ...

Page 10

... USB protocols and the user interfaces. The major task of the software process, that is mapped upon the microcontroller control the different modules of the UDA1321 in such a way that it behaves as a USB device. Therefore the microcontroller: Interprets the USB requests and maps them upon the ...

Page 11

... This descriptor map will be reported to the USB host during enumeration and on request. DSP The full descriptor map is implemented in the firmware exploiting the full functionality of the UDA1321. The USB descriptors and their most important fields, in relationship to the characteristics of the UDA1321 are briefly explained ) the DSP has four s below ...

Page 12

... H UMAN INTERFACE DEVICE SPECIFIC DESCRIPTORS The inputs defined on the UDA1321 are transmitted via the USB to the host according to the HID class. The host 12 Preliminary specification ...

Page 13

... Device Class Definition for Audio Devices” ) upon the actual volume setting of the USB DAC. When using the UDA1321, the range is 0 down (in steps of 1 dB) and dB. Independant control of ‘left’/’right’ volume is possible ...

Page 14

... Note 1. The volume control characteristics of this table are in accordance with the latest Audio Device Class Definition. The volume control characteristics of the UDA1321/N101 are slightly different; see Chapter “USB-DAC UDA1321/N101 (Firmware sw 2.1.1.7)” M UTE CONTROL Mute is one of the sound features as defined in the “USB Device Class Definition for Audio Devices” ...

Page 15

... It should be noted that the negative treble values as defined in the “USB Device Class Definition for Audio Devices” are not supported by the UDA1321; the 0 dB value is returned as 0 dB. Table 4 gives the mapping of the bTreble value upon the actual treble setting of the USB DAC. ...

Page 16

... Device Class Definition for Audio Devices” are not supported by the UDA1321; the 0 dB value is returned as 0 dB. The maximum Bass value which will be reported to the host is always 24 dB independent of the mode. The maximum mode is the most accurate mode when the Bass values are reported to the host ...

Page 17

... If the maximum of the bass plus volume gives clipping, the Bass is reduced. Clipping prevention is selectable via the configuration map. De-emphasis De-emphasis is one of the properties which is not supported by the USB. De-emphasis for 44.1 kHz can be predefined in the configuration map selected at start-up of the UDA1321. 17 Preliminary specification BASS USB DAC (dB) SIDE (dB) minimum flat 19 ...

Page 18

... EEPROM and if an EEPROM is detected, the internal descriptors are overwritten and the selected port configuration is applied EEPROM is detected, the UDA1321 tries to read the logical levels of GP3 and GP0. A choice can be made from four configuration maps via these two pins. ...

Page 19

Acrobat reader. white to force landscape pages to be ... SDA t BUF t LOW t r SCL t HD;STA t HD;DAT P S ...

Page 20

... Philips Semiconductors Universal Serial Bus (USB) Digital-to-Analog Converter (DAC) Table 6 Control options for the UDA1321 via the EEPROM configuration map; note 1 BYTE REGISTER (HEX) NAME ASR control register 3 ADAC mode register 0 1998 Oct 06 COMMENTS recognition pattern; do not change it recognition pattern ...

Page 21

... GP3 Usage Page if HID selected GP3 Usage if HID selected reserved reserved GP4 Usage Page if HID selected GP4 Usage if HID selected reserved 21 Preliminary specification UDA1321 BIT VALUE and lock after 512 samples 01 = lock after 2048 samples 10 = lock after 4096 samples ...

Page 22

... USB DAC idVendor high byte idVendor low byte idProduct high byte idProduct low byte bmAttributes maximum power steps with maximum 500 mA 22 Preliminary specification UDA1321 BIT VALUE HID output LED output 2 (activated when DBB is active) 4 ...

Page 23

... The serial number is only supported in the external configuration map and not in the four internal configuration maps. The general purpose pins (GP0 to GP5) The UDA1321 has 6 General Purpose (GP) pins; these are pins GP0 to GP5. These can be used either for digital I/O functions or for general purposes. The configurations presented are as implemented in the standard firmware. ...

Page 24

... HID input 2 HID input 1 standby; note 4 mute; note 5 FUNCTION 1 connect/disconnect BCKO WSO DO DI HID input 1 24 Preliminary specification UDA1321 FUNCTION 2 connect/disconnect HID input 3 HID input 2 HID input 1 HID/LED output 2; note 6 HID/LED output 1; note 6 FUNCTION 2 connect/disconnect BCKO WSO DO DI ...

Page 25

... S-bus data protocol and the LSB-justified serial data input format with word lengths of 16, 18 and 20 bits. Using the 4-pins digital I/O-bus the UDA1321 device acts as a master, controlling the BCK and WS signals. The period of the WS signal is determined by the number of samples in the 1 ms frame of the USB. This implies that the WS signal does not have a constant period time, but is jittery ...

Page 26

... WS RIGHT t BCK( BCK T cy DATA 1998 Oct Fig.8 Overall filter characteristics of the UDA1321. t s;WS t h;WS t BCK( LSB Fig.9 Timing of digital I/O input signals. 26 Preliminary specification MGM110 100 f (kHz) LEFT t s;DAT t h ...

Page 27

Acrobat reader. white to force landscape pages to be ... WS LEFT BCK DATA MSB B2 WS LEFT BCK DATA WS ...

Page 28

... THERMAL CHARACTERISTICS SYMBOL PARAMETER R thermal resistance from junction to ambient th(j-a) QFP64 SDIP32 SO28 1998 Oct 06 CONDITIONS MIN. 0 note 1 3000 note 2 300 CONDITIONS in free air 28 Preliminary specification UDA1321 TYP. MAX. UNIT 125 C +150 +3000 V +300 V resistor. VALUE UNIT 48 ...

Page 29

... LI C input capacitance i 1998 Oct 06 PARAMETER = 48 MHz 44.1 kHz; unless otherwise specified. osc s CONDITIONS note 1 note ground pin to ground pin to ground 29 Preliminary specification UDA1321 MIN. TYP. MAX. 3.0 3.3 3 MIN. TYP. MAX. 3.0 3.3 3.6 3.0 3.3 3.6 3.0 3.3 3 ...

Page 30

... Notes 1. This value depends strongly on the application. The specified value is the typical value obtained using the application as given in Fig.12 start-up of the oscillator. 3. The power-save mode (power management) is not supported in the UDA1321/N101; see Chapter “USB-DAC UDA1321/N101 (Firmware sw 2.1.1.7)”. 1998 Oct 06 CONDITIONS MIN ...

Page 31

... Oct MHz 44.1 kHz; unless otherwise specified. osc s CONDITIONS steady-state drive 31 Preliminary specification UDA1321 MIN. TYP. MAX 110 1.3 2 11.97 12.00 12.03 0.9995 1.0000 1.0005 3.5 0.0 +3 ...

Page 32

... DDO V channel unbalance o crosstalk between channels ct 1998 Oct 06 CONDITIONS 2 C-bus); see Fig.7 notes 2 and 3 kHz; ripple V = 0.1 V ripple(p-p) maximum volume Preliminary specification UDA1321 MIN. TYP. MAX. 0 100 4.7 4.0 4.7 4.0 4.7 4.0 5.0 0.9 250 1000 300 400 48 50 13.5 23.0 30.5 450 700 1450 ...

Page 33

... Use for calculation of the power-on reset set-up time the C 4. The audio information from the USB interface is fed directly to the ADAC. APPLICATION INFORMATION The UDA1321 is designed to be used as a self-powered device. 2 The I C-bus EEPROM is optional and can be used e.g. to program your own Vendor ID and Product ID. In order to help customers with defining there own configuration map, a special program called ‘ ...

Page 34

... It should be noted that the negative treble values as defined in the “USB Device Class Definition for Audio Devices” are not supported by the UDA1321; the 0 dB value is returned as 0 dB. Table 4 gives the mapping of the bTreble value upon the actual treble setting of the USB DAC. ...

Page 35

... Preliminary specification TREBLE USB DAC (dB) SIDE (dB) minimum flat 0. 0.25 0.50 0.75 1.00 1. 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3. ... 5. ... 7. ... 9. ... 31. UDA1321 maximum ...

Page 36

... C14 100 nF V SSA V DDA ( UDA1321H SSI V DDI V SSE V DDE C16 C18 100 nF 100 nF L11 L12 (63 V) (63 V) BLM32A07 BLM32A07 C17 C15 100 nF 100 (63 V) (63 V) R16 R17 UDA1321 ...

Page 37

... PCX8582X SDA 4 5 C22 C12 100 (63 V) (16 V) C10 47 F (16 V) audio output C11 47 F (16 V) BCK digital WS output DO MGM843 37 Preliminary specification UDA1321 ...

Page 38

... XTAL2 1 MHz XTAL1 4.7 pF Pin numbers in parenthesis represent the UDA1321PS. (1) BLM32A07. 3 100 nF 100 nF 100 nF 100 nF (1) (1) (1) 100 nF 100 nF 100 nF V SSI V DDI V SSE V DDE V SSX V DDX ...

Page 39

... 0.50 0.25 20.1 14.1 24.2 1 0.35 0.14 19.9 13.9 23.6 REFERENCES JEDEC EIAJ 39 Preliminary specification 18.2 1.0 1.95 0.2 0.2 0.1 17.6 0.6 EUROPEAN PROJECTION UDA1321 SOT319 detail X (1) ( 1.2 1 0.8 0.8 0 ISSUE DATE 95-02-04 97-08-01 ...

Page 40

... EIAJ MS-013AE 40 Preliminary specification detail 10.65 1.1 1.1 0.25 0.25 1.4 10.00 0.4 1.0 0.419 0.043 0.043 0.055 0.01 0.01 0.394 0.016 0.039 EUROPEAN PROJECTION UDA1321 SOT136 ( 0.9 0.1 0 0.035 0.004 0.016 ISSUE DATE 95-01-24 97-05-22 ...

Page 41

... IEC SOT232-1 1998 Oct scale (1) ( 1.3 0.53 0.32 29.4 9.1 0.8 0.40 0.23 28.5 8.7 REFERENCES JEDEC EIAJ 41 Preliminary specification 3.2 10.7 12.2 1.778 10.16 2.8 10.2 10.5 EUROPEAN PROJECTION UDA1321 SOT232 ( max. 0.18 1.6 ISSUE DATE 92-11-17 95-02-04 ...

Page 42

... A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. The longitudinal axis of the package footprint must be parallel to the solder flow. The package footprint must incorporate solder thieves at the downstream end. 42 Preliminary specification UDA1321 CAUTION ...

Page 43

... components conveys a license under the Philips’ system provided the system conforms to the I 43 Preliminary specification UDA1321 2 C patent to use the 2 C specification defined by ...

Page 44

Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, ...

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