uda1351h NXP Semiconductors, uda1351h Datasheet

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uda1351h

Manufacturer Part Number
uda1351h
Description
96 Khz Iec 958 Audio Dac
Manufacturer
NXP Semiconductors
Datasheet

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Product specification
Supersedes data of 2000 Feb 18
File under Integrated Circuits, IC01
DATA SHEET
UDA1351H
96 kHz IEC 958 audio DAC
INTEGRATED CIRCUITS
2000 Jul 27

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uda1351h Summary of contents

Page 1

... DATA SHEET UDA1351H 96 kHz IEC 958 audio DAC Product specification Supersedes data of 2000 Feb 18 File under Integrated Circuits, IC01 INTEGRATED CIRCUITS 2000 Jul 27 ...

Page 2

... LIMITING VALUES 10 THERMAL CHARACTERISTICS 11 CHARACTERISTICS 12 TIMING CHARACTERISTICS 13 APPLICATION INFORMATION 14 PACKAGE OUTLINE 15 SOLDERING 15.1 Introduction to soldering surface mount packages 15.2 Reflow soldering 15.3 Wave soldering 15.4 Manual soldering 15.5 Suitability of surface mount IC packages for wave and reflow soldering methods 16 DATA SHEET STATUS 17 DEFINITIONS 18 DISCLAIMERS 2 Product specification UDA1351H ...

Page 3

... BCKO and WSO signals are output 2 – I S-bus or LSB-justified 16, 20 and 24 bits formats are supported. When the UDA1351H is clock slave of the data input interface: – BCK and WS signals are input 2 – I S-bus or LSB-justified 16, 20 and 24 bits formats are supported. ...

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... A-weighted f = 1.0 kHz tone at 96 kHz dB; A-weighted f = 1.0 kHz tone code = 0; A-weighted f = 1.0 kHz tone code = 0; A-weighted f = 1.0 kHz tone 1.0 kHz tone 0 Product specification UDA1351H TYP. MAX. UNIT 3.0 3.6 V 3.0 3.6 V 8.0 mA 750 A 0.7 mA 1.0 mA 16.0 mA 24.5 mA 2 ...

Page 5

... DATAI Fig.1 Block diagram DDA(DAC) V ref V DDA VOUTL V SSA(DAC) VOUTR DAC DAC NOISE SHAPER INTERPOLATOR AUDIO FEATURE PROCESSOR DATA INPUT INTERFACE BCKI SELCLK WSI SELSPDIF Product specification UDA1351H VERSION SOT307 MUTE 1 RESET MGL976 ...

Page 6

... DIU static pin control selection input S-bus data output S-bus word select output not connected DISD test pin 2; must be connected to digital ground (V not connected 6 Product specification UDA1351H DESCRIPTION ) SSD DDD ) SSD ) ...

Page 7

... Schmitt-triggered input and output A analog reference voltage AI analog input AO analog output 2000 Jul 27 (1) TYPE not connected DO IEC 958 input pre-emphasis output 0 DS digital supply voltage DID test pin; must be connected to digital ground (V DESCRIPTION 7 Product specification UDA1351H DESCRIPTION ) SSD ...

Page 8

... V DDD(C) V SSD V SSD(C) L3DATA L3CLOCK DATAI BCKI WSI L3MODE n.c. 2000 Jul UDA1351H Fig.2 Pin configuration. 8 Product specification UDA1351H 33 BCKO V DDA(PLL SSA(PLL PREEM1 29 CLKOUT 28 n.c. V DDA 27 V SSA 26 V SSA(DAC ref 23 TC MGL977 ...

Page 9

... The UDA1351H is a low cost multi-purpose IEC 958 decoder DAC with a variety of operating modes. In modes and 4 the UDA1351H is clock master; it generates the clock for both the outgoing and incoming digital data streams. Consequently, any device providing data for the UDA1351H via the data input interface in mode 4 will be slave to the clock generated by the UDA1351H ...

Page 10

... An example is given in Fig.3 where V power supply and V 8.3 The UDA1351H is equipped with a cosine roll-off mute in the DSP data path of the DAC part. Muting the DAC, by pin MUTE (in static mode) or via bit MT (in L3 mode) will result in a soft mute as presented in Fig.4. The cosine roll-off soft mute takes 32 sampling frequency of 44 ...

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... IEC 958 INPUT The UDA1351H IEC 958 decoder can select 1 out of 2 IEC 958 input channels. An on-chip amplifier with hysteresis amplifies the IEC 958 input signal to CMOS level (see Fig.5). handbook, halfpage ...

Page 12

... Soft mute control with raised cosine roll-off De-emphasis selection of the incoming data stream for f = 32.0, 44.1 and 48.0 kHz. s 2000 Jul 27 8.5.5 The UDA1351H includes an on-board interpolating filter which converts the incoming data stream from 1f by cascading a recursive filter and a FIR filter. Table 2 Interpolator characteristics PARAMETER Pass-band ripple Stop band ...

Page 13

Acrobat reader. white to force landscape pages to be ... WS LEFT BCK DATA MSB B2 MSB 2 ...

Page 14

... Control The UDA1351H can be controlled by means of static pins or via the L3 interface. For optimum use of the features of the UDA1351H the L3 control mode is recommended since only basic functions are available in the static pin control mode. It should be noted that the static pin control mode and L3 control mode are mutual exclusive. In the static pin control mode pins L3MODE and L3DATA are used to select the format for the data output and input interface ...

Page 15

... L3 CONTROL MODE The L3 control mode allows maximum flexibility in controlling the UDA1351H. It should be noted that in the L3 control mode several base-line functions are still controlled by pins on the device and that on start-up in the L3 control mode the output is explicitly muted by bit MT via the L3 interface. Also it should be noted that in using the L3 control mode, an initialization string is needed after power-up of the device for reliable operation ...

Page 16

... IEC 958 audio DAC 8.7 L3 interface 8.7.1 G ENERAL The UDA1351H has an L3 microcontroller interface and all the digital sound processing features and various system settings can be controlled by a microcontroller. The controllable settings are: Restoring L3 defaults Power-on Selection of input channel, clock source, DAC input and ...

Page 17

Acrobat reader. white to force landscape pages to be ... L3 wake-up pulse after power-up L3CLOCK L3MODE device address L3DATA 0 1 DOM bits ...

Page 18

... Table 6): 1. One byte starting with ‘01’ for signalling the write action to the device, followed by the device address (‘011000’ for the UDA1351H) 2. One byte starting with a ‘0’ for signalling the write action, followed by 7 bits indicating the destination ...

Page 19

... I NITIALIZATION STRING For proper and reliable operation it is needed that the UDA1351H is initialized in the L3 control mode. This is needed to have the PLL start up after power-up of the device under all conditions. The initialization string is given in Table 8. Table 8 L3 init string and set defaults after power-up. ...

Page 20

... Acrobat reader. white to force landscape pages to be ... 8.7 VERVIEW OF INTERFACE REGISTERS Table 9 UDA1351H register map ADDR FUNCTION D15 D14 D13 D12 D11 Writable settings 00H system PON parameters ...

Page 21

... A 1-bit value to select the source for clock regeneration, either from the IEC 958 input or digital data input interface. In the event that the IEC 958 input is used as a clock source the UDA1351H is clock master on the digital data output and input interfaces. Table 12 Clock source selection ...

Page 22

... Product specification UDA1351H Soft mute FUNCTION 0 no muting 1 muting (default setting) Volume control VC4 VC3 VC2 VC1 VC0 VOLUME (dB ...

Page 23

... PLL lock FUNCTION 0 out-of-lock 1 locked SPDIF lock detection SPD lock FUNCTION 0 not locked or non-PCM data detected 1 locked and PCM data detected Audio sample frequency detection ASF0 FUNCTION 0 0 44.1 kHz 0 1 undefined 1 0 48.0 kHz 1 1 32.0 kHz Product specification UDA1351H ...

Page 24

... V output short-circuited to V which can withstand ESD pulses of 1600 to +1600 V. SSA(PLL DAC operation after short-circuiting cannot be warranted. DD CONDITIONS in free air 24 Product specification UDA1351H FUNCTION 0 level II 1 level I 0 level III 1 undefined MIN. MAX. 2.7 5 ...

Page 25

... DAC in playback mode DAC in Power-down mode DAC in playback mode DAC in Power-down mode measured with respect to V SSA note 3 25 Product specification UDA1351H MIN. TYP. MAX. 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 8.0 750 ...

Page 26

... all voltages measured with respect to ground; unless L CONDITIONS f = 32.0 kHz 44.1 kHz 48.0 kHz 96.0 kHz cycle time of sample s frequency 26 Product specification UDA1351H MIN. TYP. MAX 100 95 100 96 0.4 0.1 0.2 0.5 3.3 6 ...

Page 27

... L3DATA hold time in data h(L3)R transfer mode 2000 Jul 27 CONDITIONS MIN 500 250 250 190 190 190 190 190 190 30 read mode 50 read mode 360 27 Product specification UDA1351H TYP. MAX. UNIT ...

Page 28

... L3MODE t h(L3)A L3CLOCK L3DATA 2000 Jul 27 t h(WS su(WS) t BCKL t d(DATAO-WS) 2 Fig.9 I S-bus timing of output and input interface. t CLK(L3)L t CLK(L3)H t su(L3)A t su(L3)DA t h(L3)DA BIT 0 Fig.10 Timing for address mode. 28 Product specification UDA1351H t d(DATAO-BCK) t h(DATAO) t su(DATAI) t h(DATAI) MGS756 t su(L3)A t h(L3)A T cy(CLK)(L3) BIT 7 MGL723 ...

Page 29

... Philips Semiconductors 96 kHz IEC 958 audio DAC handbook, full pagewidth t stp(L3) L3MODE t su(L3)D L3CLOCK L3DATA write L3DATA read t en(L3)DA 2000 Jul 27 t CLK(L3)L T cy(CLK)L3 t CLK(L3)H t h(L3)DA t su(L3)DA BIT 0 t su(L3)R t h(L3)R Fig.11 Timing for data transfer mode. 29 Product specification UDA1351H t stp(L3) t h(L3)D t h(L3)DA BIT 7 t dis(L3)DA MGL889 ...

Page 30

... J2 V DDD V DDD 100 F 100 F 100 F (16 V) (16 V) (16 V) AGND DGND C42 UDA1351H R39 C9 C28 pre- I S-bus I S-bus 100 nF emphasis output input (50 V) ...

Page 31

... 2.5 scale (1) ( 0.40 0.25 10.1 10.1 12.9 0.8 0.20 0.14 9.9 9.9 12.3 REFERENCES JEDEC EIAJ detail 12.9 0.95 1.3 0.15 0.15 0.1 12.3 0.55 EUROPEAN PROJECTION Product specification UDA1351H SOT307 (1) ( 1.2 1 0.8 0.8 0 ISSUE DATE 95-02-04 97-08-01 ...

Page 32

... Use a low voltage ( less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 32 Product specification UDA1351H ...

Page 33

... Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2000 Jul 27 SOLDERING METHOD WAVE not suitable (2) not suitable suitable (3)(4) not recommended (5) not recommended 33 Product specification UDA1351H (1) REFLOW suitable suitable suitable suitable suitable ...

Page 34

... Product specification UDA1351H (1) These products are not Philips Semiconductors ...

Page 35

... Philips Semiconductors 96 kHz IEC 958 audio DAC 2000 Jul 27 NOTES 35 Product specification UDA1351H ...

Page 36

Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. + 101 ...

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