adv7390 Analog Devices, Inc., adv7390 Datasheet - Page 47

• Manufacturer Part Number: adv7390
• Description: Low Power, Chip Scale 10-bit Sd/hd Video Encoder
• Manufacturer: Analog Devices, Inc.

SD VCR FF/RW SYNC
Subaddress 0x82, Bit 5
In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW sync control bit can be used for non-
standard input video, that is, in fast forward or rewind modes.
In fast forward mode, the sync information at the start of a new
field in the incoming video usually occurs before the correct
number of lines/fields is reached. In rewind mode, this sync
signal usually occurs after the total number of lines/fields is
reached. Conventionally, this means that the output video has
corrupted field signals because one signal is generated by the
incoming video and another is generated when the internal
line/field counters reach the end of a field.
When the VCR FF/RW sync control is enabled (Subaddress 0x82,
Bit 5), the line/field counters are updated according to the
incoming VSYNC signal and when the analog output matches
the incoming VSYNC signal.
This control is available in all slave-timing modes except
Slave Mode 0.
VERTICAL BLANKING INTERVAL
Subaddress 0x31, Bit 4; Subaddress 0x83, Bit 4
The ADV739x is able to accept input data that contains vertical
blanking interval (VBI) data (such as CGMS, WSS, VITS) in
SD, ED, and HD modes.
If VBI is disabled (Subaddress 0x31, Bit 4 for ED/HD;
Subaddress 0x83, Bit 4 for SD), VBI data is not present at the
output and the entire VBI is blanked. These control bits are
valid in all master and slave timing modes.
For the SMPTE 293M (525p) standard, VBI data can be
inserted on Line 13 to Line 42 of each frame, or on Line 6 to
Lind 43 for the ITU-R BT.1358 (625p) standard.
1
2
3
4
5
FOR EXAMPLE, VCR OR CABLE.
F
SEQUENCE BIT
RESET ADV739x DDS.
REFER TO THE ADV7390/ADV7391 AND ADV7392/ADV7393 “INPUT CONFIGURATION” TABLES FOR PIXEL DATA PIN ASSIGNMENTS.
F
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
SC
SC
RTC
PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV73xx F
PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS.
Figure 64. SD Subcarrier Frequency Lock Timing and Connections Diagram (Subaddress 0x84, Bits [2:1] = 11)
H/L TRANSITION
COUNT START
COMPOSITE
VIDEO
TIME SLOT 01
128
1
LOW
ADV7403
VIDEO
DECODER
13
LCC1
SUBCARRIER
14 BITS
PHASE
P19 TO
SFL
P10
14
0
4 BITS
RESERVED
21
19
Rev. 0 | Page 47 of 96
CLKIN
SFL/MISO
PIXEL PORT
SAMPLE
VALID
ADV739x
F
SC
SC
VBI data can be present on Line 10 to Line 20 for NTSC and on
Line 7 to Line 22 for PAL.
In SD Timing Mode 0 (slave option), if VBI is enabled, the
blanking bit in the EAV/SAV code is overwritten. It is possible
to use VBI in this timing mode as well.
If CGMS is enabled and VBI is disabled, the CGMS data is
nevertheless available at the output.
SD SUBCARRIER FREQUENCY REGISTERS
Subaddress 0x8C to Subaddress 0x8F
Four 8-bit registers are used to set up the subcarrier frequency.
The value of these registers is calculated using the following
equation:
where the sum is rounded to the nearest integer.
For example, in NTSC mode:
where:
Subcarrier Register Value = 569408543d = 0×21F07C1F
SD F
SD F
SD F
SD F
PLL INCREMENT
DDS REGISTER IS
5
ADV7390/ADV7391/ADV7392/ADV7393
INVALID
SAMPLE
SC
SC
SC
SC
DAC 1
DAC 2
DAC 3
Subcarrier
Subcarrier
Number
Number
Register 0: 0x1F
Register 1: 0x7C
Register 2: 0xF0
Register 3: 0x21
2
of
of
Frequency
Register
27
subcarrier
SEQUENCE
8/LINE
LOCKED
CLOCK
MHz
0
BIT
Value
clock
3
Register
6768
5 BITS
RESERVED
periods
RESERVED
=
RESET BIT
cycles
⎛
⎜
⎝
227
1716
=
in
in
5 .
one
4
one
⎞
⎟
⎠
×
video
2
video
32
=
line
569408543
line
×
2
32