adv7390 Analog Devices, Inc., adv7390 Datasheet - Page 93

• Manufacturer Part Number: adv7390
• Description: Low Power, Chip Scale 10-bit Sd/hd Video Encoder
• Manufacturer: Analog Devices, Inc.

Table 107. 16-Bit 720p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
Table 108. 16-Bit 720p YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
Table 109. 16-Bit 720p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
Table 110. 16-Bit 720p YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
Table 111. 16-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
Setting
0x02
0x1C
0x10
0x2C
0x01
Setting
0x02
0x1C
0x10
0x28
0x01
Setting
0x02
0x1C
0x10
0x10
0x2C
0x01
Setting
0x02
0x1C
0x10
0x10
0x28
0x01
Setting
0x02
0x1C
0x10
0x6C
0x01
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
720p @ 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
720p @ 60 Hz/59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
RGB output enabled. RGB output sync
enabled.
720p @ 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
RGB output enabled. RGB output sync
enabled.
720p @ 60 Hz/59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
1080i @ 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Rev. 0 | Page 93 of 96
Table 112. 16-Bit 1080i YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
Table 113. 16-Bit 1080i YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
Table 114. 16-Bit 1080i YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
Table 115. 8-Bit 720p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
Table 116. 10-Bit 720p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
0x33
ADV7390/ADV7391/ADV7392/ADV7393
Setting
0x02
0x1C
0x10
0x18
0x01
Setting
0x02
0x1C
0x10
0x10
0x6C
0x01
Setting
0x02
0x1C
0x10
0x10
0x18
0x01
Setting
0x02
0x1C
0x20
0x2C
0x01
Setting
0x02
0x1C
0x20
0x2C
0x01
0x6C
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
1080i @ 30 Hz/29.97 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
RGB output enabled. RGB output sync
enabled.
1080i @ 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
RGB output enabled. RGB output sync
enabled.
1080i @ 30 Hz/29.97 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
720p @ 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
720p @ 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
10-bit input enabled.