epm7128bti100-7 Altera Corporation, epm7128bti100-7 Datasheet

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epm7128bti100-7

Manufacturer Part Number
epm7128bti100-7
Description
Programmable Logic Device
Manufacturer
Altera Corporation
Datasheet

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Features...
Altera Corporation
DS-MAX7000B-3.5
September 2005, ver. 3.5
Usable gates
Macrocells
Logic array blocks
Maximum user I/O
pins
t
t
t
t
f
PD
SU
FSU
CO1
CNT
Table 1. MAX 7000B Device Features
(ns)
(ns)
(ns)
(ns)
(MHz)
Feature
f
EPM7032B
303.0
600
3.5
2.1
1.0
2.4
32
36
2
For information on in-system programmable 5.0-V MAX 7000S or 3.3-V
MAX 7000A devices, see the
Data Sheet
High-performance 2.5-V CMOS EEPROM-based programmable logic
devices (PLDs) built on second-generation Multiple Array MatriX
(MAX
Advanced 2.5-V in-system programmability (ISP)
Pin-compatible with the popular 5.0-V MAX 7000S and 3.3-V
MAX 7000A device families
High-density PLDs ranging from 600 to 10,000 usable gates
3.5-ns pin-to-pin logic delays with counter frequencies in excess
of 303.0 MHz
Programs through the built-in IEEE Std. 1149.1 Joint Test Action
Group (JTAG) interface with advanced pin-locking capability
Enhanced ISP algorithm for faster programming
ISP_Done bit to ensure complete programming
Pull-up resistor on I/O pins during in-system programming
ISP circuitry compliant with IEEE Std. 1532
or the
EPM7064B
®
) architecture (see
1,250
303.0
®
3.5
2.1
1.0
2.4
64
68
4
MAX 7000A Programmable Logic Device Family Data
EPM7128B
MAX 7000 Programmable Logic Device Family
2,500
243.9
Table
128
100
4.0
2.5
1.0
2.8
8
1)
EPM7256B
Programmable Logic
5,000
188.7
256
164
5.0
3.3
1.0
3.3
16
MAX 7000B
EPM7512B
Data Sheet
10,000
163.9
512
212
Device
5.5
3.6
1.0
3.7
32
Sheet.
1

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epm7128bti100-7 Summary of contents

Page 1

... FSU t (ns) 2.4 CO1 f (MHz) 303.0 CNT Altera Corporation DS-MAX7000B-3.5 ® High-performance 2.5-V CMOS EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX ® (MAX ) architecture (see Table – Pin-compatible with the popular 5.0-V MAX 7000S and 3.3-V MAX 7000A device families – ...

Page 2

... Pin-compatibility with other MAX 7000B devices in the same package Advanced software support – Software design support and automatic place-and-route provided by Altera’s MAX+PLUS Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations TM , 0.8-mm Ultra ® II development system for Altera Corporation ...

Page 3

... MAX 7000B devices are available in a wide range of packages, including PLCC, BGA, FineLine BGA, 0.8-mm Ultra FineLine BGA, PQFP, TQFP, and TQFP packages. See Altera Corporation MAX 7000B Programmable Logic Device Data Sheet – Additional design entry and simulation support provided by ...

Page 4

... Pin 0.8-mm Pin (4) TQFP Ultra PQFP FineLine BGA (3) 100 100 120 141 164 120 141 176 TM pin-out feature. Therefore, “SameFrame Pin-Outs” on “SameFrame Pin-Outs” on page 14 Altera Corporation 256- 256-Pin Pin FineLine BGA BGA (4) 100 164 212 212 for more ...

Page 5

... The MAX 7000B architecture includes four dedicated inputs that can be used as general-purpose inputs or as high-speed, global control signals (clock, clear, and two output enable signals) for each macrocell and I/O pin. Altera Corporation MAX 7000B Programmable Logic Device Data Sheet LABs Macrocells ...

Page 6

... Direct input paths from I/O pins to the registers that are used for fast setup times Output Enables (1) LAB Macrocells I Control Block LAB Macrocells I Control Block Altera Corporation I I/O ...

Page 7

... XOR gates) to implement combinatorial functions secondary inputs to the macrocell’s register preset, clock, and clock enable control functions. Two kinds of expander product terms (“expanders”) are available to supplement macrocell logic resources: ■ ■ Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Figure 2 Global Global Clear Clocks ...

Page 8

... Array clock implemented with a product term. In this mode, the flipflop can be clocked by signals from buried macrocells or I/O pins. Figure 1, these global clock signals can be the true or the complement of Figure 2, the product-term select matrix allocates product terms Altera Corporation ...

Page 9

... A small delay (t shareable expanders are used. can feed multiple macrocells. Figure 3. MAX 7000B Shareable Expanders Shareable expanders can be shared by any or all macrocells in an LAB. Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Figure 3 36 Signals 16 Shared ...

Page 10

... Within each group of eight, the lowest-numbered macrocell can only lend parallel expanders and the highest-numbered macrocell can only borrow them. borrowed from a neighboring macrocell For example macrocell requires 14 product PEXP PEXP Figure 4 shows how parallel expanders can be . Altera Corporation ...

Page 11

... Only the signals required by each LAB are actually routed from the PIA into the LAB. into the LAB. An EEPROM cell controls one input to a two-input AND gate, which selects a PIA signal to drive into the LAB. Altera Corporation MAX 7000B Programmable Logic Device Data Sheet From Previous ...

Page 12

... MAX 7000B devices. The I/O control block has six or ten global output enable signals that are driven by the true or complement of two output enable signals, a subset of the I/O pins subset of the I/O macrocells. 12 PIA Signals To LAB . Figure 6 shows the I/O CC Altera Corporation ...

Page 13

... The MAX 7000B architecture provides dual I/O feedback, in which macrocell and pin feedbacks are independent. When an I/O pin is configured as an input, the associated macrocell can be used for buried logic. Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Global Output Enable Signals (1) ...

Page 14

... Figure 7. SameFrame Pin-Out Example 14 Printed Circuit Board Designed for 256-Pin FineLine BGA Package 100-Pin FineLine BGA 100-Pin FineLine BGA Package (Reduced I/O Count or Logic Requirements) Figure 7). 256-Pin FineLine BGA 256-Pin FineLine BGA Package (Increased I/O Count or Logic Requirements) Altera Corporation ...

Page 15

... Application Note 122 (Using STAPL for ISP & ICR via an Embedded The ISP circuitry in MAX 7000B devices is compliant with the IEEE Std. 1532 specification. The IEEE Std. 1532 is a standard developed to allow concurrent ISP between multiple PLD vendors. Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Application Note 88 and Processor) ...

Page 16

... ISP mode to user mode. The exit ISP stage requires 1 ms. A pulse time to erase, program, or read the EEPROM cells. A shifting time based on the test clock (TCK) frequency and the number of TCK cycles to shift instructions, address, and data into the device. Altera Corporation ...

Page 17

... The time required to program a single MAX 7000B device in-system can be calculated from the following formula: t PROG where: t The ISP times for a stand-alone verification of a single MAX 7000B device can be calculated from the following formula: t VER where: t Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Cycle PTCK = t + ------------------------------- - PPULSE f ...

Page 18

... MHz 500 kHz 0.01 0.01 0.02 0.01 0.02 0.04 0.02 0.04 0.07 0.03 0.08 0.15 0.06 0.15 0.30 Tables 4 through 6 are associated Stand-Alone Verification t (s) VPULSE 0.002 0.002 0.002 0.002 0.002 200 kHz 100 kHz 2.26 2.47 2.82 2.36 2.72 3.32 2.56 3.23 4.34 3.05 4.45 6.78 3.95 6.69 11.26 200 kHz 100 kHz 0.04 0.09 0.18 0.07 0.18 0.35 0.14 0.35 0.69 0.30 0.76 1.51 0.60 1.50 3.00 Altera Corporation Cycle VTCK 18,000 35,000 69,000 151,000 300,000 Units 50 kHz 3.52 s 4.52 s 6.56 s 11.44 s 20.40 s Units 50 kHz 0.36 s 0.70 s 1.38 s 3.02 s 6.00 s ...

Page 19

... These instructions are used when programming MAX 7000B devices via the JTAG ports with the MasterBlaster or ByteBlasterMV download cable, or using a Jam File (.jam), Jam Byte-Code File (.jbc), or Serial Vector Format File (.svf) via an embedded processor or test equipment. Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Altera Programming Hardware Data Programming Hardware Manufacturers ...

Page 20

... JTAG boundary-scan testing. shows the timing information for the JTAG signals. Tables 7 and 8 Boundary-Scan Register Length 96 192 288 480 624 Note (1) IDCODE (32 Bits) Manufacturer’s Identity (11 Bits) 00001101110 00001101110 00001101110 00001101110 00001101110 Altera Corporation show the 1 (1 Bit) ( ...

Page 21

... Figure 8. MAX 7000B JTAG Waveforms Captured Table 9 devices. Symbol Note: (1) Altera Corporation MAX 7000B Programmable Logic Device Data Sheet TMS TDI t JCP t t JCH JCL TCK t JPZX TDO t JSSU Signal JSZX Signal to Be Driven shows the JTAG timing parameters and values for MAX 7000B Table 9. JTAG Timing Parameters & ...

Page 22

... VCCIO pins are connected to a 3.3-V power supply, the output high is at 3.3 V and is therefore compatible with 3.3-V or 5.0-V systems. Devices operating with V adder. Table and t parameters. EN SEXP levels of 2 1.8 V incur a nominal timing delay CCIO describes the MAX 7000B MultiVolt I/O support. ) for the LPA LAD LAC IC ACL Altera Corporation , CC ...

Page 23

... The slew rate control affects both the rising and falling edges of the output signal. Advanced I/O Standard Support The MAX 7000B I/O pins support the following I/O standards: LVTTL, LVCMOS, 1.8-V I/O, 2.5-V I/O, GTL+, SSTL-3 Class I and II, and SSTL-2 Class I and II. Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Input Signal (V) 2.5 3.3 5.0 ...

Page 24

... I/O bank. Table 11. Macrocell Pins Contained in Each I/O Bank Device EPM7032B EPM7064B EPM7128B EPM7256B EPM7512B level. Any I/O pin that uses one of the voltage-referenced standards REF Individual Power Bus Bank 1 Bank 2 1-16 17-32 1-32 33-64 1-64 65-128 1-128, 177-181 129-176, 182-256 1-265 266-512 Altera Corporation ...

Page 25

... V recommended operation conditions. When transitioning from ISP to User Mode with bus hold enabled, the bus-hold circuit captures the value present on the pin at the end of programming. Altera Corporation MAX 7000B Programmable Logic Device Data Sheet level. CCIO to prevent overdriving signals ...

Page 26

... Input Setup Time to CLK—Bused Signal parameter. However, these devices are within that parameter. EPM7256B and EPM7512B devices meet all other 66-MHz PCI timing specifications. Drive to VCCIO level R BH I/O Table 13 shows the MAX 7000B Specification 66-MHz PCI - Altera Corporation (1) (1) ...

Page 27

... EEPROM bit and all internal logic elements ensures 100% programming yield. AC test measurements are taken under conditions equivalent to those shown in erased during early stages of the production flow. Altera Corporation MAX 7000B Programmable Logic Device Data Sheet and V power planes can be powered in any ...

Page 28

... Device Output 600 Ω [481 Ω] Device input rise and fall S2 times < Note (1) Min Max –0.5 3.6 –0.5 3.6 –2.0 4.6 –33 50 –65 150 –65 135 –65 135 Altera Corporation To Test System C1 (includes jig capacitance) Unit ° C ° C ° C ...

Page 29

... Output voltage O T Ambient temperature A T Junction temperature J t Input rise time R t Input fall time F Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Conditions (10) (3) For commercial use For industrial use (11) For commercial use For industrial use (11) Min Max Unit 2 ...

Page 30

... OL CCIO V = –0.5 to 3 –0.5 to 3 1.7 to 3.6 V (8) CCIO Min Max Unit 2.0 3.9 V 1.7 3.9 V × 0.65 3 CCIO –0.5 0.8 V –0.5 0.7 V × –0.5 0.35 V CCIO 2 – V CCIO 0.2 2.1 V 2.0 V 1.7 V 1.2 V 0.4 V 0.2 V 0.2 V 0.4 V 0.7 V 0.4 V μ – μ – k¾ Altera Corporation ...

Page 31

... The device is fully initialized within the POR time after V (11) These devices support in-system programming for –40° to 100° C. For in-system programming support between –40° and 0° C, contact Altera Applications. Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Note (9) ...

Page 32

... Room Temperature Current (mA 1.8-V VCCIO 150 I OL 120 CCINT V = 1.8 V CCI O Room Temperature Output Voltage (V) O 150 I OL 120 CCINT V = 2.5 V CCI O Room Temperature Output Voltage ( Altera Corporation 3 4 ...

Page 33

... External timing parameters, which represent pin-to-pin timing delays, can be calculated as the sum of internal parameters. between internal and external delay parameters. f See information. Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Internal Output Enable Delay t IOE Global Control ...

Page 34

... PIA Clock into Logic Array Clock at Register Data from Logic Array t to Logic Array to Pin t PIA t SEXP LAC LAD t PEXP t COMB ACL PIA CLR t OD Altera Corporation PIA PRE t OD ...

Page 35

... Maximum internal global CNT clock frequency t Minimum array clock ACNT period f Maximum internal array ACNT clock frequency Altera Corporation MAX 7000B Programmable Logic Device Data Sheet through 32 show MAX 7000B device timing parameters. Notes (1) Conditions -3.5 Min Max (2) 3 (2) 3 ...

Page 36

... CLR t PIA delay PIA t Low-power adder LPA 36 Notes (1) Conditions -3.5 Min Max 0.3 0.3 0.9 1.0 1.5 0.4 1.4 1 1.6 0.7 0.4 0.8 1.2 0.5 0.2 1.2 1.2 0.7 1.0 1.0 (2) 0.7 (4) 1.5 Speed Grade -5.0 -7.5 Min Max Min Max 0.5 0.7 0.5 0.7 1.3 2.0 1.5 1.5 2.1 3.2 0.6 0.9 2.0 3.1 1.7 2.6 0.2 0.3 1.2 1.8 6.2 6.8 2.2 3.4 7.2 8.4 2.2 3.4 1.1 1.6 0.5 0.9 0.8 1.1 1.2 1.4 0.6 0.9 0.3 0.5 1.8 2.8 1.7 2.6 1.1 1.6 1.3 1.9 1.3 1.9 1.0 1.4 2.1 3.2 Altera Corporation Unit ...

Page 37

... Input to PIA Input to global clock and clear Input to fast input register All outputs GTL+ Input to PIA Input to global clock and clear Input to fast input register All outputs Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Parameter -3.5 Min Notes (1) Speed Grade -5.0 -7.5 ...

Page 38

... The t parameter must be added to the t LPA running in low-power mode. 38 Parameter -3.5 Min , LAD LAC IC ACL CPPW Notes (1) Speed Grade -5.0 -7.5 Max Min Max Min 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 Table 15 on page 29. See , t , and t parameters for macrocells EN SEXP Altera Corporation Unit Max 0.0 ns 0.0 ns 0.0 ns 0.0 ns Figure 14 for ...

Page 39

... Minimum global clock CNT period f Maximum internal global CNT clock frequency t Minimum array clock ACNT period f Maximum internal array ACNT clock frequency Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Note (1) Conditions -3 Min Max (2) 3 (2) 3.5 (2) 2.1 0.0 (2) 1 ...

Page 40

... PIA delay PIA t Low-power adder LPA 40 Note (1) Conditions -3 Min Max 0.3 0.3 0.9 1.0 1.5 0.4 1.4 1 1.6 0.7 0.4 0.8 1.2 0.5 0.2 1.2 1.2 0.7 1.0 1.0 (2) 0.7 (4) 1.5 Speed Grade -5 -7 Min Max Min Max 0.5 0.7 0.5 0.7 1.3 2.0 1.5 1.5 2.1 3.2 0.6 0.9 2.0 3.1 1.7 2.6 0.2 0.3 1.2 1.8 6.2 6.8 2.2 3.4 7.2 8.4 2.2 3.4 1.1 1.6 0.5 0.9 0.8 1.1 1.2 1.4 0.6 0.9 0.3 0.5 1.8 2.8 1.7 2.6 1.1 1.6 1.3 1.9 1.3 1.9 1.0 1.4 2.1 3.2 Altera Corporation Unit ...

Page 41

... Input to PIA Input to global clock and clear Input to fast input register All outputs GTL+ Input to PIA Input to global clock and clear Input to fast input register All outputs Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Parameter -3 Min Note (1) Speed Grade -5 -7 ...

Page 42

... LPA running in low-power mode. 42 Parameter -3 Min , LAD LAC IC ACL CPPW Note (1) Speed Grade -5 -7 Max Min Max Min 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 Table 15 on page 29. See , t , and t parameters for macrocells EN SEXP Altera Corporation Unit Max 0.0 ns 0.0 ns 0.0 ns 0.0 ns Figure 14 for ...

Page 43

... Minimum global clock CNT period f Maximum internal global CNT clock frequency t Minimum array clock ACNT period f Maximum internal array ACNT clock frequency Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Note (1) Conditions -4 Min Max (2) 4 (2) 4.0 (2) 2.5 0.0 (2) 1 ...

Page 44

... PIA delay PIA t Low-power adder LPA 44 Note (1) Conditions -4 Min Max 0.3 0.3 1.3 1.0 1.5 0.4 1.6 1.4 0 1.8 1.0 0.4 0.8 1.2 0.5 0.2 1.4 1.4 1.1 1.0 1.0 (2) 1.0 1.5 (4) Speed Grade -7 -10 Min Max Min Max 0.6 0.8 0.6 0.8 2.9 3.7 1.5 1.5 2.8 3.8 0.8 1.0 2.9 3.8 2.6 3.4 0.3 0.4 1.7 2.2 6.7 7.2 3.3 4.4 8.3 9.4 3.3 4.4 1.9 2.6 0.8 1.1 0.9 0.9 1.6 1.6 1.1 1.4 0.3 0.4 2.8 3.6 2.6 3.4 2.3 3.1 1.9 2.6 1.9 2.6 2.0 2.8 2.8 3.8 Altera Corporation Unit ...

Page 45

... Input to PIA Input to global clock and clear Input to fast input register All outputs GTL+ Input to PIA Input to global clock and clear Input to fast input register All outputs Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Parameter -4 Min Note (1) Speed Grade -7 -10 ...

Page 46

... LPA running in low-power mode. 46 Parameter -4 Min , LAD LAC IC ACL CPPW Note (1) Speed Grade -7 -10 Max Min Max Min 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 Table 15 on page 29. See , t , and t parameters for macrocells EN SEXP Altera Corporation Unit Max 0.0 ns 0.0 ns 0.0 ns 0.0 ns Figure 14 for ...

Page 47

... Minimum global clock CNT period f Maximum internal global CNT clock frequency t Minimum array clock ACNT period f Maximum internal array ACNT clock frequency Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Note (1) Conditions -5 Min Max (2) 5 (2) 5.0 (2) 3.3 (2) 0.0 1 ...

Page 48

... PIA delay PIA t Low-power adder LPA 48 Note (1) Conditions -5 Min Max 0.4 0.4 1.5 1.5 1.5 0.4 1.7 1.5 0 2.2 1.2 0.6 0.8 1.2 0.7 0.3 1.5 1.5 1.3 1.0 1.0 (2) 1.7 2.0 (4) Speed Grade -7 -10 Min Max Min Max 0.6 0.8 0.6 0.8 2.5 3.1 1.5 1.5 2.3 3.0 0.6 0.8 2.5 3.3 2.2 2.9 0.2 0.3 1.4 1.9 6.4 6.9 3.3 4.5 8.3 9.5 3.3 4.5 1.8 2.5 1.0 1.3 1.1 1.1 1.4 1.4 1.0 1.3 0.4 0.5 2.3 3.0 2.2 2.9 2.1 2.7 1.6 2.1 1.6 2.1 2.6 3.3 3.0 4.0 Altera Corporation Unit ...

Page 49

... Input to PIA Input to global clock and clear Input to fast input register All outputs GTL+ Input to PIA Input to global clock and clear Input to fast input register All outputs Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Parameter -5 Min Note (1) Speed Grade -7 -10 ...

Page 50

... LPA running in low-power mode. 50 Parameter -5 Min , LAD LAC IC ACL CPPW Note (1) Speed Grade -7 -10 Max Min Max Min 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 Table 15 on page 29. See , t , and t parameters for macrocells EN SEXP Altera Corporation Unit Max 0.0 ns 0.0 ns 0.0 ns 0.0 ns Figure 14 for ...

Page 51

... Minimum global clock CNT period f Maximum internal global CNT clock frequency t Minimum array clock ACNT period f Maximum internal array ACNT clock frequency Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Note (1) Conditions -5 Min Max (2) 5 (2) 5.5 (2) 3.6 0.0 (2) 1 ...

Page 52

... PIA delay PIA t Low-power adder LPA 52 Note (1) Conditions -5 Min Max 0.3 0.3 2.2 1.5 1.5 0.4 1.7 1.5 0 2.8 1.5 0.4 0.8 1.2 0.5 0.2 1.8 1.5 2.0 1.0 1.0 (2) 2.4 2.0 (4) Speed Grade -7 -10 Min Max Min Max 0.3 0.5 0.3 0.5 3.2 4.0 1.5 1.5 2.1 2.7 0.5 0.7 2.3 3.0 2.0 2.6 0.2 0.2 1.2 1.6 6.2 6.6 3.8 5.0 8.8 10.0 3.8 5.0 2.0 2.6 0.5 0.7 1.1 1.1 1.4 1.4 0.7 1.0 0.3 0.4 2.4 3.1 2.0 2.6 2.8 3.6 1.4 1.9 1.4 1.9 3.4 4.5 2.7 3.6 Altera Corporation Unit ...

Page 53

... Input to PIA Input to global clock and clear Input to fast input register All outputs GTL+ Input to PIA Input to global clock and clear Input to fast input register All outputs Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Parameter -5 Min Note (1) Speed Grade -7 -10 ...

Page 54

... P INT IO CCINT CC value, which depends on the device output load characteristics IO Note (1) Speed Grade -7 -10 Max Min Max Min 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 Table 15 on page 29. See , t , and t parameters for macrocells EN SEXP , in MHz) for MAX 7000B MAX IO Altera Corporation Unit Max 0.0 ns 0.0 ns 0.0 ns 0.0 ns Figure 14 for ...

Page 55

... LAB with no output load. Actual I because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions. Altera Corporation MAX 7000B Programmable Logic Device Data Sheet value depends on the switching frequency and the application CCINT ...

Page 56

... Typical I CC Active (mA 100 EPM7032B High Speed 153.8 MHz Low Power 250 150 200 Frequency (MHz) EPM7064B High Speed 153.8 MHz Low Power 150 200 250 Frequency (MHz) Altera Corporation 285.7 MHz 300 285.7 MHz 300 ...

Page 57

... Figure 17. I Figure 18. I Altera Corporation MAX 7000B Programmable Logic Device Data Sheet vs. Frequency for EPM7128B Devices CC 220 VCC = 2.5 V 200 Room Temperature 180 160 140 Typical I CC 120 Active (mA) 100 100 vs. Frequency for EPM7256B Devices CC 400 VCC = 2.5 V Room Temperature ...

Page 58

... MAX 7000B Programmable Logic Device Data Sheet Figure 19 vs. Frequency for EPM7512B Devices CC 700 VCC = 2.5 V Room Temperature 600 500 400 Typical I CC Active (mA) 300 Low Power 200 100 EPM7512B 163.9 MHz High Speed 99.0 MHz 80 100 120 140 160 180 Frequency (MHz) Altera Corporation ...

Page 59

... I/O /TDI 8 I/O 9 I/O 10 GND 11 I/O EPM7032B 12 I/O 13 I/O/TMS EPM7064B 14 I/O 15 VCC 16 I 44-Pin PLCC Altera Corporation MAX 7000B Programmable Logic Device Data Sheet through 29 show the package pin-out diagrams for Pin 1 39 I/O I/O/TDI 38 I/O/TDO I/O 37 I/O I/O 36 I/O GND 35 VCC I/O 34 I/O I/O 33 ...

Page 60

... N/C I/O/TDI 2 I/O 3 I/O 4 GNDIO 5 I/O / VREFA 6 7 I/O 8 I/O/TMS I/O 9 VCCIO1 48-Pin VTQFP EPM7032B EPM7064B G EPM7128B 36 I/O 35 I/O/TDO 34 I/O 33 I/O 32 VCCIO2 31 I/O EPM7032B 30 I/O EPM7064B 29 I/O/TCK 28 I/O / VREFB 27 GNDIO 26 I/O 25 I/O A1 Ball Pad Corner Altera Corporation ...

Page 61

... Figure 23. 100-Pin TQFP Package Pin-Out Diagram Figure 24. 100-Pin FineLine BGA Package Pin-Out Diagram Package outline not drawn to scale. Indicates location of Ball A1 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet Package outline not drawn to scale. Pin 1 Pin 26 EPM7064B EPM7128B EPM7256B Pin 76 ...

Page 62

... Package outline not drawn to scale. Indicates Location of Ball A1 EPM7128AE 62 . Package outline not drawn to scale Indicates location of Pin 1 Pin 1 Pin Pin 109 EPM7128B EPM7256B EPM7512B Pin Altera Corporation A1 Ball Pad Corner ...

Page 63

... Figure 27. 208-Pin PQFP Package Pin-Out Diagram Package outline not drawn to scale Pin 1 Pin 53 Altera Corporation MAX 7000B Programmable Logic Device Data Sheet . EPM7256B EPM7512B Pin 157 Pin 105 63 ...

Page 64

... MAX 7000B Programmable Logic Device Data Sheet Figure 28. 256-Pin BGA Package Pin-Out Diagram Package outline not drawn to scale. Indicates Location of Ball A1 EPM7512B Altera Corporation A1 Ball Pad Corner ...

Page 65

... The following changes were made to the MAX 7000B Programmable Logic Device Family Data Sheet version 3.5: ■ Version 3.4 The following changes were made to the MAX 7000B Programmable Logic Device Family Data Sheet version 3.4: ■ Altera Corporation MAX 7000B Programmable Logic Device Data Sheet . ...

Page 66

... Innovation Drive San Jose, CA 95134 Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the (408) 544-7000 stylized Altera logo, specific device designations, and all other words and logos that are identified as http://www.altera.com ...

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