atv2500h-35pi ATMEL Corporation, atv2500h-35pi Datasheet - Page 8

• Manufacturer Part Number: atv2500h-35pi
• Description: High-density Uv-erasable Programmable Logic Device - Atmel Corporation
• Manufacturer: ATMEL Corporation

Preload and Observability of Registered Outputs
The ATV2500H/L's registers are provided with circuitry to
allow loading of each register asynchronously with either a
high or a low. This feature will simplify testing since any
state can be forced into the registers to control test
sequencing. A V
appropriate register high; a V
of the polarity or other configuration bit settings.
The preload state is entered by placing an 11V to 14V sig-
nal on pin 38 on the DIP and pin 42 on the SMP. When the
Power-Up Reset
The registers in the ATV2500H/L are designed to reset dur-
ing power-up. At a point delayed slightly from V
3.8V, all registers will be reset to the low state. The output
state will depend on the polarity of the output buffer.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how V
lowing conditions are required:
1. The V
2. After reset occurs, all input and feedback setup
3. The signals from which the clock is derived must
8
Level forced on Odd
I/O pin during
preload cycle.
times must be met before driving the clock term
high,
remain stable during t
CC
V
V
V
V
V
V
V
V
IH
IH
IH
IH
IL
IL
IL
IL
rise must be monotonic,
IH
level on the Odd I/O pins will force the
CC
ATV2500H/L
actually rises in the system, the fol-
PR
pin state
Q Select
.
IL
High
High
High
High
Low
Low
Low
Low
will force it low, independent
Odd select
Even/
High
High
High
High
Low
Low
Low
Low
CC
crossing
Even Q1 state
after cycle
High
Low
clock term is pulsed high, (pin 21 on the DIP, pin 23 on the
SMP) the data on the I/O pins is placed into the 12 regis-
ters chosen by the Q select and even/odd select pins.
Register 2 observability mode is entered by placing an 11V
to 14V signal on pin 2 (DIP or SMP). In this mode, the con-
tents of the buried register bank will appear on the associ-
ated outputs when the OE control signals are active.
X
X
X
X
X
X
Parameter
t
PR
Even Q2 state
after cycle
Description
Power-Up
Reset Time
High
Low
X
X
X
X
X
X
Odd Q1 state
Min
after cycle
High
Low
X
X
X
X
X
X
Typ
600
Max
1000
Odd Q2 state
after cycle
High
Low
X
X
X
X
X
X
Units
ns