adsp-2186bca-160 Analog Devices, Inc., adsp-2186bca-160 Datasheet

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... DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities and on-chip program and data memory. The ADSP-2186 integrates 40K bytes of on-chip memory con- figured as 8K words (24-bit) of program RAM and 8K words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery operated portable equip- ment ...

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... ADSP-218x based evaluation board with PC monitor software plus Assembler, Linker, Simulator and PROM Splitter software. The ADSP-21xx EZ-KIT Lite is a low cost, easy to use hardware platform on which you can quickly get started with your DSP soft- ware design. The EZ-KIT Lite includes the following features: • ...

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... The ADSP-2186 incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Here is a brief list of the capabilities of the ADSP-2186 SPORTs. For additional information on Serial Ports, refer to the ADSP- 2100 Family User’s Manual, Third Edition. ...

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... SPORT configuration determined by the DSP System Control Register. Soft- ware configurable. Memory Interface Pins The ADSP-2186 processor can be used in one of two modes: Full Memory Mode, which allows BDMA operation with full external overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities ...

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... The CLKOUT pin may also be disabled to reduce external power dissipation. Power-Down The ADSP-2186 processor has a low power feature that lets the processor enter a very low power dormant state through hard- ware or software control. Following is a brief list of power-down features. Refer to the ADSP-2100 Family User’s Manual, Third Edition, “ ...

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... ADSP-2186 Idle When the ADSP-2186 is in the Idle Mode, the processor waits indefinitely in a low power state until an interrupt occurs. When an unmasked interrupt occurs serviced; execution then continues with the instruction following the IDLE instruction. In Idle mode IDMA, BDMA and autobuffer cycle steals still occur ...

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... Clock Signals The ADSP-2186 can be clocked by either a crystal or a TTL- compatible clock signal. The CLKIN input cannot be halted, changed during operation or operated below the specified frequency during normal opera- tion. The only exception is while the processor is in the power- down state. For additional information, refer to Chapter 9, ADSP-2100 Family User’ ...

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... EXTERNAL 0x0000 Figure 5. Program Memory (Mode Data Memory The ADSP-2186 has 8160 16-bit words of internal data memory. In addition, the ADSP-2186 allows the use of 8K external memory overlays. Figure 6 shows the organization of the data memory. DATA MEMORY ADDRESS 32 MEMORY– MAPPED REGISTERS ...

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... Internal Memory DMA Port (IDMA Port; Host Memory Mode) The IDMA Port provides an efficient means of communication between a host system and the ADSP-2186. The port is used to access the on-chip program memory and data memory of the DSP with only one DSP cycle per word overhead. The IDMA port cannot, however, be used to write to the DSP’ ...

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... The IDLE instruction can also be used to allow the processor to hold off execution while booting continues through the BDMA interface. For BDMA accesses while in Host Mode, the addresses to boot memory must be constructed externally to the ADSP-2186. The only memory address bit provided by the processor is A0. –10– BDMA feature is used to load ...

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... Note: Pins PF0, PF1 and PF2 are also used for device configu- ration during reset. REV. A BIASED ROUNDING A mode is available on the ADSP-2186 to allow biased round- ing in addition to the normal unbiased rounding. When the BIASRND bit is set to 0, the normal unbiased rounding opera- tions occur. When the BIASRND bit is set to 1, biased round- ing occurs instead of the normal unbiased rounding ...

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... These pins have no function except during emulation, and do not require pull-up or pull-down resistors. The traces for these signals between the ADSP-2186 and the connector must be kept as short as pos- sible, no longer than three inches. The following pins are also used by the EZ-ICE: ...

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... DSP components statisti- cally vary in switching characteristics and timing requirements within published limits. Restriction: All memory strobe signals on the ADSP-2186 (RD, WR, PMS, DMS, BMS, CMS and IOMS) used in your target system must have 10 k pull-up resistors connected when the EZ-ICE is being used ...

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... V on BR, CLKIN Inactive. 9 Idle refers to ADSP-2186 state of operation during execution of IDLE instruction. Deasserted pins are driven to either measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 12, 13, 14), 30% are type 2 DD and type 6, and 20% are idle instructions ...

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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-2186 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

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... ADSP-2186 TIMING PARAMETERS Parameter Clock Signals and Reset Timing Requirements: t CLKIN Period CKI t CLKIN Width Low CKIL t CLKIN Width High CKIH Switching Characteristics: t CLKOUT Width Low CKL t CLKOUT Width High CKH t CLKIN High to CLKOUT High CKOH Control Signals Timing Requirements: RESET Width Low ...

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... IFS IFH following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-2100 Family User’s Manual, Third Edition, for further informa- tion on interrupt servicing.) 2 Edge-sensitive interrupts require pulsewidths greater than 10 ns ...

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... asynchronous signal meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on 1 the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition, for BR/BG cycle relationships. 2 BGH is asserted when the bus is granted and the processor requires control of the bus to continue. ...

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... Min 1 0.5 t – 0.25 t – 0.25 t – 0.25 t – 0.5 t – RDA t ASR RWR CRD t t RDD RDH t AA Figure 14. Memory Read –19– ADSP-2186 Max Unit 0.5 t – 0.75 t – ...

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... ADSP-2186 Parameter Memory Write Switching Characteristics: Data Setup before WR High t DW Data Hold after WR High Pulsewidth Low to Data Enabled t WDE A0–A13, xMS Setup before WR Low t ASW Data Disable before Low t DDR CLKOUT High to WR Low t CWR A0–A13, xMS, Setup before WR Deasserted ...

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... SCS SCH SCDD t SCDV t SCDH t SCDE t TDE t TDV t RDV t TDE t TDV t RDV Figure 16. Serial Ports –21– ADSP-2186 Min Max 0. SCK t SCP t SCP Unit ...

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... ADSP-2186 Parameter IDMA Address Latch Timing Requirements: t Duration of Address Latch IALP t IAD15–0 Address Setup before Address Latch End IASU t IAD15–0 Address Hold after Address Latch End IAH IACK Low before Start of Address Latch t IKA t Start of Write or Read after Address Latch End ...

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... If Write Pulse ends after IACK Low, use specifications t IACK IS IWR IAD15–0 REV. A Min IDSU IDH , t . IKSU IKH t IKW t IKHW t IWP t IDH t IDSU DATA Figure 18. IDMA Write, Short Write Cycle –23– ADSP-2186 Max Unit ...

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... If Write Pulse ends before IACK Low, use specifications Write Pulse ends after IACK Low, use specifications This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual. IACK IS IWR IAD15–0 ...

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... IKHR t IKR t IRK t t IKDS IRDE PREVIOUS READ DATA DATA t IRDV t IRDH Figure 20. IDMA Read, Long Read Cycle –25– ADSP-2186 Min Max Unit 0.5 t – – – 5 ...

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... ADSP-2186 Parameter IDMA Read, Short Read Cycle Timing Requirements: IACK Low before Start of Read t IKR t Duration of Read IRP Switching Characteristics: IACK High after Start of Read t IKHR t IAD15–0 Data Hold after End of Read IKDH t IAD15–0 Data Disabled after End of Read ...

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... MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL DD MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 12, 13, 14), 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS. 4 IDLE REFERS TO ADSP-2186 STATE OF OPERATION DURING EXECUTION OF IDLE 2 INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER MHz = 80 mW ...

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... ADSP-2186 CAPACITIVE LOADING Figures 24 and 25 show the capacitive loading characteristics of the ADSP-2186 + 4. 100 150 200 C – Figure 24. Typical Output Rise Time vs. Load Capacitance, C (at Maximum Ambient Operating Temperature NOMINAL – ...

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... CASE PD = Power Dissipation Thermal Resistance (Case-to-Ambient Thermal Resistance (Junction-to-Ambient Thermal Resistance (Junction-to-Case) JC Package JA LQFP 50 C/W 2 C/W Mini-BGA 70.7 C/W 7.4 C/W REV. A 10k 1k 100 C/W 63.3 C –29– ADSP-2186 100 TEMPERATURE – C Figure 29. Power-Down Supply Current 120 ...

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... A13/IAD12 11 GND 12 13 CLKIN XTAL 14 VDD 15 CLKOUT 16 GND 17 VDD BMS 21 DMS 22 PMS 23 IOMS 24 CMS 25 100-Lead LQFP Package Pinout ADSP-2186 TOP VIEW (Not to Scale) –30– 75 D15 74 D14 73 D13 72 D12 71 GND 70 D11 69 D10 VDD 66 GND D7/IWR 63 D6/IRD D5/IAL ...

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... The ADSP-2186 package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when Mode sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in brackets [ ּ ] are state bits latched from the value of the pin at the deassertion of RESET. ...

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... D10 GND VDD D4 GND NC GND VDD VDD D1/IAD14 EBG BR EBR EINT ELOUT ELIN EMS ECLK EE ADSP-2186 Mini-BGA (CA) Package Pinout Bottom View GND NC D20 D23 VDD GND NC PWD D19 D21 VDD A7/IAD6 PF2 PF1 D13 ...

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... The ADSP-2186 Mini-BGA package pinout is shown in the table below. Pin names in bold text replace the plain text named func- tions when Mode sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET. ...

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... Part Number Range ADSP-2186KST-115 +70 C ADSP-2186BST-115 – +85 C ADSP-2186KST-133 +70 C ADSP-2186BST-133 – +85 C ADSP-2186KST-160 +70 C ADSP-2186BST-160 – +85 C ADSP-2186BCA-160 – +85 C *ST = Plastic Thin Quad Flatpack (LQFP Mini-BGA. ORDERING GUIDE Instruction Rate (MHz) 28.8 28.8 33.3 33.3 40.0 40.0 40.0 OUTLINE DIMENSIONS Dimensions shown in inches and (mm) ...

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... SQ 0.390 (9.90) 0.346 0.398 (10.10) (8.80) BSC 0.394 (10.00) SQ TOP VIEW 0.390 (9.90) 0.031 (0.80) BSC DETAIL A 0.010 (0.25) MAX 0.014 (0.35) 0.012 (0.30) 0.010 (0.25) –35– ADSP-2186 0.031 (0.80) BSC 0.346 (8.80) BSC DETAIL A 0.030 (0.75) 0.028 (0.70) 0.026 (0.65) 0.018 (0.45) ...

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