adsp-21160m Analog Devices, Inc., adsp-21160m Datasheet

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adsp-21160m

Manufacturer Part Number
adsp-21160m
Description
Sharc Dsp Microcomputer
Manufacturer
Analog Devices, Inc.
Datasheet

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SHARC is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
SUMMARY
High-Performance 32-Bit DSP—Applications in Audio,
Super Harvard Architecture—Four Independent Buses
Backwards-Compatible—Assembly Source Level
Single-Instruction-Multiple-Data (SIMD) Computational
Integrated Peripherals—Integrated I/O Processor,
Medical, Military, Graphics, Imaging, and
Communication
for Dual Data Fetch, Instruction Fetch, and
Nonintrusive, Zero-Overhead I/O
Compatible with Code for ADSP-2106x DSPs
Architecture—Two 32-Bit IEEE Floating-Point
Computation Units, Each with a Multiplier, ALU,
Shifter, and Register File
4 M Bit On-Chip Dual-Ported SRAM, Glueless
Multiprocessing Features, and Ports (Serial, Link,
External Bus, and JTAG)
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One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700
Fax:781/326-8703
KEY FEATURES
80 MHz (12.5 ns) Core Instruction Rate
Single-Cycle Instruction Execution, Including SIMD
480 MFLOPS Peak and 320 MFLOPS Sustained
Dual Data Address Generators (DAGs) with Modulo and
Zero-Overhead Looping and Single-Cycle Loop Setup,
IEEE 1149.1 JTAG Standard Test Access Port and
400-Ball 27
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Operations in Both Computational Units
Performance (Based on FIR)
Bit-Reverse Addressing
Providing Efficient Program Sequencing
On-Chip Emulation
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adsp-21160m Summary of contents

Page 1

... One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A. Tel:781/329-4700 Fax:781/326-8703 SHARC DSP Microcomputer ADSP-21160M 27 mm Metric PBGA Package -7$* 7(67 ,2 3257 (08/$7,21 '$7$ $''5 '$7$ $''5 (;7(51$/ ,2' ,2$ 3257   $''5 %86 08; 08/7,352&(6625 ,17(5)$&( '$7$ %86 08; +267 3257 '0$ ,23 & ...

Page 2

... Glueless Connection to Asynchronous and SBSRAM External Memories MHz Operation GENERAL DESCRIPTION The ADSP-21160M SHARC DSP is the first processor in a new family featuring Analog Devices’ Super Harvard Architecture. Easing portability, the ADSP-21160M is application source code compatible with first generation ADSP-2106x SHARC DSPs in SISD (Single Instruction, Single Data) mode. To take advantage of the processor’ ...

Page 3

... ADSP-21160M Family Core Architecture The ADSP-21160M includes the following archi- tectural features of the ADSP-2116x family core. The ADSP-21160M is code compatible at the assembly level with the ADSP-21060, ADSP-21061, and ADSP-21062. SIMD Computational Engine The ADSP-21160M contains two computational process- ing elements that operate as a Single Instruction Multiple Data (SIMD) engine ...

Page 4

... External bus packing to 16-, 32-, 48-, or 64-bit words is performed during DMA transfers. Fourteen channels of DMA are available on the ADSP-21160M—six via the link ports, four via the serial ports, and four via the processor’s external port (for either –4– ...

Page 5

... Maximum throughput for interprocessor data transfer is 320M bytes/s over the external port. Broadcast writes allow simultaneous transmission of data to all ADSP-21160Ms and can be used to implement reflective semaphores. Six link ports provide for a second method of multiprocess- ing communications. Each link port can support communications to another ADSP-21160M ...

Page 6

... Phased Locked Loop The ADSP-21160M uses an on-chip PLL to generate the internal clock for the core. Ratios of 2:1, 3:1, and 4:1 between the core and CLKIN are supported. The CLK_CFG pins are used to select the ratio. The CLKIN rate is the rate at which the synchronous external port operates ...

Page 7

... Maintain a one-to-one correspondence with the tool’s command line switches. Analog Devices’ DSP emulators use the IEEE 1149.1 JTAG test access port of the ADSP-21160M processor to monitor and control the target board processor during emulation. 1 development envi- ...

Page 8

... ADSP-2116x Family core architecture and instruction set, refer to the ADSP-2116x SHARC DSP Hardware Reference. PIN FUNCTION DESCRIPTIONS ADSP-21160M pin definitions are listed below. Inputs identified as synchronous (S) must meet timing require- ments with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST). – ...

Page 9

... ADSP-21160M internal memory multiprocessing system, RDH is driven by the bus master. Memory Write Low Strobe. WRL is asserted when ADSP-21160M writes to the low word of external memory or internal memory of other ADSP-21160Ms. External devices must assert WRL for writing to ADSP-21160M’s low word of internal memory. ...

Page 10

... ADSP-21160M’s external bus. When HBR is asserted in a multiprocessing system, the ADSP-21160M that is bus master will relinquish the bus and assert HBG. To relinquish the bus, the ADSP-21160M places the address, data, select, and strobe lines in a high impedance state. HBR has priority over all ADSP-21160M bus requests (BR6– multiprocessing system ...

Page 11

... Priority Access. Asserting its PA pin allows an ADSP-21160M bus slave to interrupt background DMA transfers and gain access to the external bus connected to all ADSP-21160Ms in the system. If access priority is not required in a system, the PA pin should be left unconnected. Data Transmit (Serial Ports 0, 1). Each DT pin has internal pull-up resistor. ...

Page 12

... Test Data Output (JTAG). Serial scan output of the boundary scan path. Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-21160M. TRST has internal pull-up resistor. Emulation Status. Must be connected to the ADSP-21160M emulator target board connector only ...

Page 13

... ADSP-21160M SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Signal K Grade Parameter V Internal (Core) Supply Voltage DDINT AV Analog (PLL) Supply Voltage DD V External (I/O) Supply Voltage DDEXT V High Level Input Voltage IH1 V High Level Input Voltage IH2 V Low Level Input Voltage IL T Case Operating Temperature CASE 1 Specifications subject to change without notice ...

Page 14

... DDINHIGH composite average based on a range of low activity code. DDINLOW 15 Idle denotes ADSP-21160M state during execution of IDLE instruction. 16 Characterized, but not tested. 17 Applies to all signal pins. 18 Guaranteed, but not tested. ...

Page 15

... Timing Specifications The ADSP-21160M’s internal clock switches at higher fre- quencies than the system input clock (CLKIN). To generate the internal clock, the DSP uses an internal phase-locked loop (PLL). This PLL-based clocking minimizes the skew between the system clock (CLKIN) signal and the DSP’s internal clock (the clock source for the external port logic and I/O pads) ...

Page 16

... VDD and CLKIN (not including start-up time of external clock oscillator). 2 Only required if multiple ADSP-21160Ms must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple ADSP-21160Ms communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset ...

Page 17

... Only required for IRQx recognition in the following cycle. 2 Applies only if t and t requirements are not met. SIR HIR Timer Table 7. Timer Parameter Switching Characteristic: t CLKIN High to TIMEXP DTEX REV Figure 12. Interrupts Figure 13. Timer –17– ADSP-21160M Min Max 6 0 2+t CK Min Max 1 7 Unit Unit ns ...

Page 18

... ADSP-21160M Flags Table 8. Flags Parameter Timing Requirements: t FLAG3–0 IN Setup Before CLKIN High SFI t FLAG3–0 IN Hold After CLKIN High HFI t FLAG3–0 IN Delay After RDx/WRx Low DWRFI t FLAG3–0 IN Hold After RDx/WRx Deasserted HFIWR Switching Characteristics: t FLAG3–0 OUT Delay After CLKIN High ...

Page 19

... Memory Read—Bus Master Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-21160M is the bus master accessing external Table 9. Memory Read—Bus Master Parameter Timing Requirements: t Address, CIF, Selects Delay to Data ...

Page 20

... ADSP-21160M Memory Write—Bus Master Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-21160M is the bus master accessing external Table 10. Memory Write—Bus Master Parameter Timing Requirements: t ACK Delay from Address, Selects ...

Page 21

... REV. 0 Figure 16. Memory Write—Bus Master –21– ADSP-21160M ...

Page 22

... ADSP-2116x SHARC DSP Hardware Reference. When accessing a slave ADSP-21160M, these switching characteristics must meet the slave’s timing requirements for synchronous read/writes (see Read/Write—Bus Slave on page ADSP-21160M must also meet these (bus master) timing requirements for data and acknowledge setup and hold times. 20). 1 ...

Page 23

... REV. 0 Figure 17. Synchronous Read/Write—Bus Master –23– ADSP-21160M ...

Page 24

... ADSP-21160M Synchronous Read/Write—Bus Slave Use these specifications for ADSP-21160M bus master accesses of a slave’s IOP registers or internal memory (in multiprocessor memory space). The bus master must meet these (bus slave) timing requirements. Table 12. Synchronous Read/Write—Bus Slave Parameter Timing Requirements: ...

Page 25

... REV. 0 Figure 18. Synchronous Read/Write—Bus Slave –25– ADSP-21160M ...

Page 26

... ADSP-21160M Multiprocessor Bus Request and Host Bus Request Use these specifications for passing of bus mastership between multiprocessing ADSP-21160Ms (BRx host processor (HBR, HBG). Table 13. Multiprocessor Bus Request and Host Bus Request Parameter Timing Requirements: t HBG Low to RDx/WRx/CS Valid HBGRCSV t HBR Setup Before CLKIN ...

Page 27

... REV. 0 Figure 19. Multiprocessor Bus Request and Host Bus Request –27– ADSP-21160M ...

Page 28

... RDYPRD t Data Disable After RDx High HDARWH Figure 20. Read Cycle (Asynchronous Read—Host to ADSP-21160M) is returned by the ADSP-21160M, the host can drive the RDx and WRx pins to access the ADSP-21160M’s internal and Table 15) for asyn- memory or IOP registers. HBR and HBG are assumed low for this timing – ...

Page 29

... Data Setup Before WRx High SDATWH t Data Hold After WRx High HDATWH Switching Characteristics: t REDY (O/D) or (A/D) Low Delay After WRx/CS Low DRDYWRL t REDY (O/D) or (A/D) Low Pulsewidth for Write RDYPWR Figure 21. Write Cycle (Asynchronous Write—Host to ADSP-21160M) REV. 0 Min – ...

Page 30

... ADSP-21160M Three-State Timing—Bus Master and Bus Slave These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to CLKIN and the SBTS pin. This timing is appli- cable to bus master transition cycles (BTC) and host transition cycles (HTC) as well as the SBTS pin. ...

Page 31

... REV. 0 Figure 22. Three-State Timing—Bus Slave, HBR, SBTS –31– ADSP-21160M ...

Page 32

... ADSP-21160M DMA Handshake These specifications describe the three DMA handshake modes. In all three modes DMAR is used to initiate trans- fers. For handshake mode, DMAG controls the latching or enabling of data externally. For external handshake mode, the data transfer is controlled by the ADDR31–0, RDx, WRx, PAGE, MS3– ...

Page 33

... REV. 0 Figure 23. DMA Handshake Timing –33– ADSP-21160M ...

Page 34

... ADSP-21160M Link Ports Calculation of link receiver data setup and hold relative to link clock is required to determine the maximum allowable skew that can be introduced in the transmission path between LDATA and LCLK. Setup skew is the maximum delay that can be introduced in LDATA relative to LCLK (setup skew = t Min – ...

Page 35

... LACK Low Delay After LCLK High DLALC 1 LACK goes low with t relative to rise of LCLK after first nibble, but doesn’t go low if the receiver’s link buffer is not about to fill. DLALC REV. 0 Min 2.5 2.5 t LCLK 6.0 6 Figure 24. Link Ports—Receive –35– ADSP-21160M Max Unit ...

Page 36

... ADSP-21160M Table 20. Link Ports—Transmit Parameter Timing Requirements: t LACK Setup Before LCLK High SLACH t LACK Hold After LCLK High HLACH Switching Characteristics: t Data Delay After LCLK High DLDCH t Data Hold After LCLK High HLDCH t LCLK Width Low LCLKTWL t LCLK Width High ...

Page 37

... TFS Delay After TCLK (Internally Generated TFS) DFSI t TFS Hold After TCLK (Internally Generated TFS) HOFSI REV 1 RFS Setup Before RCLK 1 –37– ADSP-21160M Min Max 3 CCLK Min Max 8 1 6.5 3 Min Max 13 3 Min Max ...

Page 38

... ADSP-21160M Table 25. Serial Ports—Internal Clock (Continued) Parameter t Transmit Data Delay After TCLK DDTI t Transmit Data Hold After TCLK HDTI t TCLK/RCLK Width SCLKIW 1 Referenced to drive edge. Table 26. Serial Ports—Enable and Three-State Parameter Switching Characteristics: t Data Enable from External TCLK DDTEN ...

Page 39

... REV. 0 Figure 26. Serial Ports –39– ADSP-21160M ...

Page 40

... ADSP-21160M Table 27. Serial Ports—External Late Frame Sync Parameter Switching Characteristics: t Data Delay from Late External TFS or External RFS with DDTLFSE MCE = 1, MFD = 0 t Data Enable from late FS or MCE = 1, MFD = 0 DDTENFS 1 MCE = 1, TFS enable and TFS valid follow and t ...

Page 41

... System Outputs = DATA63–0, ADDR31–0, MS3–0, RDx, WRx, ACK, PAGE, CLKOUT, HBG, REDY, DMAG1, DMAG2, BR6–1, PA, BRST, CIF, FLAG3–0, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, BMS. REV Figure 28. IEEE 11499.1 JTAG Test Access Port –41– ADSP-21160M Min Max ...

Page 42

... ADSP-21160M Output Drive Currents Figure 29 shows typical I–V characteristics for the output drivers of the ADSP-21160M. The curves represent the current drive capability of the output drivers as a function of output voltage. Figure 29. ADSP-21160M Typical Drive Currents Power Dissipation Total power dissipation has two components, one due to internal circuitry and one due to the switching of external output drivers ...

Page 43

... The load capacitance should include the processor’s package capacitance (C ). The switching frequency IN includes driving the load high and then back low. Address and data pins can drive high and low at a maximum rate of Table 29. ADSP-21160M Operation Types vs. Input Current Operation Peak Activity Instruction Type Multifunction Instruction Fetch ...

Page 44

... EXT system, first calculate t . Maximum INT Choose – the difference between the ADSP-21160M’s output voltage and the input threshold for the device requiring the hold time. A typical –V will be 0 the total bus capacitance (per data line), and I L total leakage or three-state current (per data line) ...

Page 45

... The ADSP-21160M is tested for performance over the commercial temperature range, 0°C to 85°C. Thermal Characteristics The ADSP-21160M is packaged in a 400-ball Plastic Ball Grid Array (PBGA). The ADSP-21160M is specified for a case temperature (T specification is not exceeded, a heatsink and/or an air flow source may be used. Use the center block of ground pins (PBGA balls: H8– ...

Page 46

... ADSP-21160M = + CASE AMB • Case temperature (measured on top surface CASE of package) • Power dissipation in W (this value depends upon the specific application; a method for calculating PD is shown under Power Dissipation). • = Value from Table 31. CA • = 6.46°C/W JB Table 31. Airflow Over Package Versus Airflow (Linear Ft ...

Page 47

... F15 V G15 DDINT F16 V G16 DDEXT F17 L1DAT[2] G17 F18 L2DAT[6] G18 F19 L2DAT[4] G19 F20 L2CLK G20 –47– ADSP-21160M Pin Name PBGA Pin# DATA[28] D01 DATA[25] D02 DATA[20] D03 DATA[19] D04 DATA[12] D05 V D06 DDEXT V D07 DDINT V D08 DDEXT ...

Page 48

... ADSP-21160M Table 32. 400-ball Metric PBGA Pin Assignments (Continued) Pin Name PBGA Pin# Pin Name DATA[44] J01 CLK_CFG_0 K01 DATA[43] J02 DATA[46] DATA[42] J03 DATA[45] DATA[41] J04 DATA[47] V J05 V DDEXT DDEXT V J06 V DDINT DDINT GND J07 GND GND J08 GND GND J09 ...

Page 49

... V15 RDH W15 V16 DMAG2 W16 V17 LBOOT W17 V18 L5DAT[1] W18 V19 L5DAT[3] W19 V20 L5DAT[5] W20 –49– ADSP-21160M Pin Name PBGA Pin# ADDR[8] Y01 ADDR[11] Y02 ADDR[13] Y03 ADDR[16] Y04 ADDR[19] Y05 ADDR[21] Y06 ADDR[24] Y07 ADDR[27] Y08 ...

Page 50

... ADSP-21160M 400-BALL METRIC PBGA PIN CONFIGURATIONS (BOTTOM VIEW, SUMMARY) –50– REV. 0 ...

Page 51

... The ADSP-21160M comes in a 27mm REV. 0 OUTLINE DIMENSIONS 27mm, 400-ball Metric PBGA package with 20 rows of balls. 400-BALL METRIC PBGA (B-400) –51– ADSP-21160M ...

Page 52

... ADSP-21160M Case Temperature 1, 2 Part Number Range ADSP-21160MKB-80 0°C to 85° Plastic Ball Grid Array (PBGA) package. 2 See ADSP-21160N data sheet for ordering information for higher-performance derivative. ORDERING GUIDE On-Chip Instruction Rate SRAM 80 MHz 4 Mbit –52– Operating Voltage 2.5 INT/3.3 EXT V ...

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