adsp-21161n Analog Devices, Inc., adsp-21161n Datasheet

adsp-21161n

Manufacturer Part Number

adsp-21161n

Description

Dsp Microcomputer

Manufacturer

Analog Devices, Inc.

Datasheet

1.ADSP-21161N.pdf (60 pages)

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registered trademarks are the property of their respective companies.

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties that

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices. Trademarks and

SUMMARY

High Performance 32-Bit DSP—Applications in Audio,

Super Harvard Architecture—Four Independent Buses

Code Compatible with All Other SHARC Family DSPs

Single-Instruction-Multiple-Data (SIMD) Computational

Serial Ports Offer I

Medical, Military, Wireless Communications,

Graphics, Imaging, Motor-Control, and Telephony

for Dual Data Fetch, Instruction Fetch, and

Nonintrusive, Zero-Overhead I/O

Architecture—Two 32-Bit IEEE Floating-Point

Computation Units, Each with a Multiplier, ALU,

Shifter, and Register File

Simultaneous Receive or Transmit Pins, which

Support up to 16 Transmit or 16 Receive Channels of

Audio

MULT

CONNECT

DAG1

BUS

(PX)

DATA

(PEX)

FILE

DAG2

40-BIT

CORE PROCESSOR

S Support Via 8 Programmable and

PM ADDRESS BUS

DM ADDRESS BUS

DM DATA BUS

PM DATA BUS

ALU

BARREL

SHIFTER

TIMER

SEQUENCER

PROGRAM

INSTRUCTION

CACHE

48-BIT

FUNCTIONAL BLOCK DIAGRAM

BARREL

SHIFTER

ALU

ADDR

PROCESSOR PORT

ADDR

DATA

(PEY)

FILE

One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel:781/329-4700

Fax:781/326-8703

Integrated Peripherals—Integrated I/O Processor,

ADSP-21161N Supports 32-Bit Fixed, 32-Bit Float, and

KEY FEATURES

100 MHz (10 ns) Core Instruction Rate

Single-Cycle Instruction Execution, Including SIMD

600 MFLOPs Peak and 400 MFLOPs Sustained

225-Ball 17 mm

DUAL-PORTED BLOCKS

40-BIT

TWO INDEPENDENT

1M Bit On-Chip Dual-Ported SRAM, SDRAM

Controller, Glueless Multiprocessing Features, and

I/O Ports (Serial, Link, External Bus, SPI, and JTAG)

40-Bit Floating-Point Formats

Operations in Both Computational Units

Performance

DATA

DUAL-PORTED SRAM

DATA

MULT

DATA

IOD

17 mm MBGA Package

DATA

(MEMORY MAPPED)

DSP Microcomputer

I/O PORT

DATA BUFFERS

REGISTERS

STATUS, &

CONTROL,

ADDR

IOP

ADDR

ADSP-21161N

IOA

I/O PROCESSOR

MULTIPROCESSOR

SERIAL PORTS (4)

LINK PORTS (2)

SPI PORTS (1)

CONTROLLER

EXTERNAL PORT

INTERFACE

AND EMULATION

HOST PORT

CONTROLLER

DMA

JTAG TEST

ADDR BUS

DATA BUS

SDRAM

FLAGS

GPIO

MUX

www.analog.com

MUX

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