adsp-2165ks-80 Analog Devices, Inc., adsp-2165ks-80 Datasheet

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adsp-2165ks-80

Manufacturer Part Number
adsp-2165ks-80
Description
Dsp Microcomputers With Rom
Manufacturer
Analog Devices, Inc.
Datasheet
a
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
GENERAL DESCRIPTION
The ADSP-216x Family processors are single-chip micro-
computers optimized for digital signal processing (DSP)
and other high speed numeric processing applications. The
ADSP-216x processors are all built upon a common core with
ADSP-2100. Each processor combines the core DSP architec-
ture—computation units, data address generators and program
sequencer—with features such as on-chip program ROM and
data memory RAM, a programmable timer and two serial ports.
The ADSP-2165/ADSP-2166 also adds program memory and
power-down mode.
This data sheet describes the following ADSP-216x Family
processors:
ADSP-2161/ADSP-2162/
ADSP-2163/ADSP-2164
ADSP-2165/ADSP-2166
SUMMARY
16-Bit Fixed-Point DSP Microprocessors with
Enhanced Harvard Architecture for Three-Bus
Independent Computation Units: ALU, Multiplier/
Single-Cycle Instruction Execution and Multifunction
On-Chip Program Memory ROM and Data Memory RAM
Integrated I/O Peripherals: Serial Ports, Timer
FEATURES
25 MIPS, 40 ns Maximum Instruction Rate (5 V)
Separate On-Chip Buses for Program and Data Memory
Program Memory Stores Both Instructions and Data
Dual Data Address Generators with Modulo and
Efficient Program Sequencing with Zero-Overhead
Double-Buffered Serial Ports with Companding Hardware,
Three Edge- or Level-Sensitive Interrupts
Low Power IDLE Instruction
PLCC and MQFP Packages
On-Chip Memory
Performance: Instruction Bus and Dual Data Buses
Accumulator and Shifter
Instructions
(Three-Bus Performance)
Bit-Reverse Addressing
Looping: Single-Cycle Loop Setup
Automatic Data Buffering and Multichannel Operation
processors with power-down and
larger on-chip memories (12K Pro-
gram Memory ROM, 1K Program
Memory RAM, 4K Data Memory
RAM)
Custom ROM-programmed DSPs:
ROM-programmed ADSP-216x
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
Fabricated in a high speed, submicron, double-layer metal
CMOS process, the highest-performance ADSP-216x proces-
sors operate at 25 MHz with a 40 ns instruction cycle time.
Every instruction can execute in a single cycle. Fabrication in
CMOS results in low power dissipation.
The ADSP-2100 Family’s flexible architecture and compre-
hensive instruction set support a high degree of parallelism.
In one cycle the ADSP-216x can perform all of the following
operations:
Table I shows the features of each ADSP-216x processor.
The ADSP-216x series are memory-variant versions of the
ADSP-2101 and ADSP-2103 that contain factory-programmed
on-chip ROM program memory. These devices offer different
amounts of on-chip memory for program and data storage.
Table I shows the features available in the ADSP-216x series of
custom ROM-coded processors.
The ADSP-216x products eliminate the need for an external
boot EPROM in your system, and can also eliminate the need
for any external program memory by fitting the entire applica-
tion program in on-chip ROM. These devices thus provide an
excellent option for volume applications where board space and
system cost constraints are of critical concern.
DATA ADDRESS
DAG 1
DSP Microcomputers with ROM
GENERATORS
Generate the next program address
Fetch the next instruction
Perform one or two data moves
Update one or two data address pointers
Perform a computation
Receive and transmit data via one or two serial ports
ALU
ARITHMETIC UNITS
ADSP-2100 CORE
DAG 2
MAC
SHIFTER
SEQUENCER
PROGRAM
FUNCTIONAL BLOCK DIAGRAM
PROGRAM MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY ADDRESS
DATA MEMORY DATA
World Wide Web Site: http://www.analog.com
SPORT 0
SERIAL PORTS
PROGRAM
MEMORY
MEMORY
SPORT 1
MEMORY
DATA
ADSP-216x
© Analog Devices, Inc., 1999
TIMER
EXTERNAL
DATA
BUS
EXTERNAL
ADDRESS
BUS

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adsp-2165ks-80 Summary of contents

Page 1

... Every instruction can execute in a single cycle. Fabrication in CMOS results in low power dissipation. The ADSP-2100 Family’s flexible architecture and compre- hensive instruction set support a high degree of parallelism. In one cycle the ADSP-216x can perform all of the following operations: • Generate the next program address • ...

Page 2

... Data Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Data Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-Down Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Entering Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Exiting Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Low Power IDLE Instruction . . . . . . . . . . . . . . . . . . . . . . . 10 ADSP-216x Prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Ordering Procedure for ADSP-216x ROM Processors . . . . 10 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SPECIFICATIONS–RECOMMENDED OPERATING CONDITIONS (ADSP-2161/ADSP-2163/ADSP-2165 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . 13 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 13 SPECIFICATIONS–SUPPLY CURRENT AND POWER (ADSP-2161/ADSP-2163/ADSP-2165) ...

Page 3

... ARCHITECTURE OVERVIEW Figure 1 shows a block diagram of the ADSP-216x architecture. The processors contain three independent computational units: the ALU, the multiplier/accumulator (MAC), and the shifter. The computational units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations ...

Page 4

... There is also a master RESET signal. Booting circuitry provides for loading on-chip program memory automatically from byte-wide external memory. After reset, three wait states are automatically generated. This allows, for example ADSP-2161 to use a 200 ns EPROM as PROGRAM DATA REGISTER MEMORY ...

Page 5

... Pin Function Descriptions show pin definitions for the ADSP- 216x processors. Any inputs not used must be tied to V SYSTEM INTERFACE Figure 3 shows a typical system for the ADSP-216x with two serial I/O devices, an optional external program and data memory. A total of 12K words of data memory and 15K words of program memory is addressable ...

Page 6

... A clock output signal (CLKOUT) is generated by the processor, synchronized to the processor’s internal cycles. Reset The RESET signal initiates a complete reset of the ADSP-216x. The RESET signal must be asserted when the chip is powered up to assure proper initialization. If the RESET signal is applied during initial power-up, it must be held long enough to allow the processor’ ...

Page 7

... Program memory may contain code and data. The external address bus is 14 bits wide. For the ADSP-216x, these lines can directly address up to 16K words, of which 2K are on-chip. ...

Page 8

... The read (RD) signal indicates a read operation and can be used as a read strobe or output enable signal. The ADSP-216x processors support memory-mapped I/O, with the peripherals memory-mapped into the data memory address space and accessed by the processor in the same manner as data memory ...

Page 9

... Three-stating the data and address buses and the PMS, DMS, BMS, RD, WR output drivers, • Asserting the bus grant (BG) signal, and halting program execution. If the Go mode is set, however, the ADSP-216x will not halt program execution until it encounters an instruction that requires an external memory access. If the ADSP-216x is performing an external memory access ...

Page 10

... IDLE state is increased by n, the clock divisor. When an enabled interrupt is received, the ADSP-216x will remain in the IDLE state for maxi- mum of n CLKIN cycles (where n = 16, 32 128) before resuming normal operation. ...

Page 11

... Instruction Set The ADSP-216x assembly language uses an algebraic syntax for ease of coding and readability. The sources and destinations of computations and data movements are written explicitly in each assembly statement, eliminating cryptic assembler mnemonics. Every instruction assembles into a single 24-bit word and executes in a single cycle ...

Page 12

... ADSP-216x Program Flow Instructions DO <addr> [UNTIL term] ; [IF cond] JUMP (Ix) ; [IF cond] JUMP <addr>; [IF cond] CALL (Ix) ; [IF cond] CALL <addr>; IF [NOT ] FLAG_IN JUMP <addr>; IF [NOT ] FLAG_IN CALL <addr>; [IF cond] SET|RESET|TOGGLE [IF cond] RTS ; [IF cond] RTI ; IDLE [(n)] ; Miscellaneous Instructions NOP ; MODIFY (Ix , My); [PUSH STS] [, POP CNTR] [, POP PC] [, POP LOOP] ; ...

Page 13

... Output pins: BG, PMS, DMS, BMS, RD, WR, A0–A13, CLKOUT, DT1, DT0 Although specified for TTL outputs, all ADSP-21xx outputs are CMOS-compatible and will drive Guaranteed but not tested. Three-stateable pins: A0–A13, D0–D23, PMS, DMS, BMS, RD, WR, DT1, SCLK1, RFS1, TFS1, DT0, SCLK0, RFS0, TFS0. ...

Page 14

... Current reflects device operating with no output loads 0.4 V and 2 Idle refers to ADSP-21xx state of operation during execution of IDLE instruction. Deasserted pins are driven to either V For typical supply current (internal power dissipation) figures, see Figure 9. Specifications subject to change without notice 51mW ...

Page 15

... load capacitance output switching frequency. Example ADSP-2161 application where external data memory is used and no other outputs are active, power dissipation is calcu- lated as follows: Assumptions: • External data memory is accessed every cycle with 50% of the address pins switching. • External data memory writes occur every other cycle with 50% of the data pins switching. • ...

Page 16

... ADSP-216x SPECIFICATIONS ADSP-2161/ADSP-2163/ADSP-2165 TEST CONDITIONS Figure 12 shows voltage reference levels for ac measurements. INPUT OUTPUT Figure 12. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) Output Disable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured out- put high or low voltage to a high impedance state ...

Page 17

... Output pins: BG, PMS, DMS, BMS, RD, WR, A0–A13, CLKOUT, DT1, DT0 All ADSP-2162, ADSP-2164 and ADSP-2166 outputs are CMOS and will drive to V Three-stateable pins: A0–A13, D0–D23, PMS, DMS, BMS, RD, WR, DT1, SCLK1, RFS1, TFS1, DT0, SCLK0, RFS0, TFS0 BR, CLKIN Active (to force three-state condition). ...

Page 18

... Current reflects device operating with no output loads 0.4 V and 2 Idle refers to ADSP-216x state of operation during execution of IDLE instruction. Deasserted pins are driven to either V For typical supply current (internal power dissipation) figures, see Figure 15. Specifications subject to change without notice ...

Page 19

... load capacitance output switching frequency. Example ADSP-2162 application where external data memory is used and no other outputs are active, power dissipation is calcu- lated as follows: Assumptions: • External data memory is accessed every cycle with 50% of the address pins switching. ...

Page 20

... ADSP-216x SPECIFICATIONS ADSP-2162/ADSP-2164/ADSP-2166 TEST CONDITIONS Figure 18 shows voltage reference levels for ac measurements. INPUT OUTPUT Figure 18. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) Output Disable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state ...

Page 21

... Timing requirements guarantee that the processor operates correctly with other devices. MEMORY REQUIREMENTS The table below shows common memory device specifications and the corresponding ADSP-216x timing parameters, for your convenience. ADSP-216x Timing Parameter Timing Parameter Definition A0– ...

Page 22

... ADSP-216x TIMING PARAMETERS (ADSP-2161/ADSP-2163/ADSP-2165) CLOCK SIGNALS AND RESET Parameter Timing Requirements: t CLKIN Period CK t CLKIN Width Low CKL t CLKIN Width High CKH RESET Width Low t RSP Switching Characteristics: t CLKOUT Width Low CPL t CLKOUT Width High CPH t CLKIN High to CLKOUT High CKOH ...

Page 23

... IFS IFH following cycle. (Refer to the “Interrupt Controller” section in Chapter 3, Program Control, of the ADSP-2100 Family User’s Manual, Third Edition for further information on interrupt servicing.) 3 Edge-sensitive interrupts require pulsewidths greater than 10 ns ...

Page 24

... Section 10.2.4, “Bus Request/Grant,” on page 212 of the ADSP-2100 Family User’s Manual, Third Edition, states that “When BR is recognized, the processor responds immediately by asserting BG during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors asserted in the cycle after BR is recognized ...

Page 25

... TIMING PARAMETERS (ADSP-2161/ADSP-2163/ADSP-2165) MEMORY READ Parameter Timing Requirements: RD Low to Data Valid t RDD A0–A13, PMS, DMS, BMS to Data Valid t AA Data Hold from RD High t RDH Switching Characteristics: RD Pulsewidth t RP CLKOUT High to RD Low t CRD A0–A13, PMS, DMS, BMS Setup Before RD Low t ASR A0– ...

Page 26

... ADSP-216x TIMING PARAMETERS (ADSP-2161/ADSP-2163/ADSP-2165) MEMORY WRITE Parameter Switching Characteristics: Data Setup Before WR High t DW Data Hold After WR High Pulsewidth Low to Data Enabled t WDE A0–A13, DMS, PMS Setup Before WR Low t ASW Data Disable Before Low t DDR CLKOUT High to WR Low ...

Page 27

... TIMING PARAMETERS (ADSP-2161/ADSP-2163/ADSP-2165) SERIAL PORTS Parameter Timing Requirements: t SCLK Period SCK t DR/TFS/RFS Setup Before SCLK Low SCS t DR/TFS/RFS Hold After SCLK Low SCH t SCLK Width SCP IN Switching Characteristics: t CLKOUT High to SCLK CC t SCLK High to DT Enable SCDE t SCLK High to DT Valid ...

Page 28

... Timing requirements guarantee that the processor operates correctly with other devices. MEMORY REQUIREMENTS The table below shows common memory device specifications and the corresponding ADSP-216x timing parameters, for your convenience. ADSP-216x Timing Parameter Timing Parameter Definition A0– ...

Page 29

... TIMING PARAMETERS (ADSP-2162/ADSP-2164/ADSP-2166) CLOCK SIGNALS AND RESET Parameter Timing Requirements: t CLKIN Period CK t CLKIN Width Low CKL t CLKIN Width High CKH RESET Width Low t RSP Switching Characteristics: t CLKOUT Width Low CPL t CLKOUT Width High CPH t CLKIN High to CLKOUT High CKOH NOTE 1 Applies after power-up sequence is complete ...

Page 30

... IFS IFH following cycle. (Refer to the “Interrupt Controller” section in Chapter 3, Program Control, of the ADSP-2100 Family User’s Manual, Third Edition, for further information on interrupt servicing.) 3 Edge-sensitive interrupts require pulse widths greater than 10 ns ...

Page 31

... Section 10.2.4, “Bus Request/Grant,” of the ADSP-2100 Family User’s Manual, Third Edition, states that, “When BR is recognized, the processor responds immedi- ately by asserting BG during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors asserted in the cycle after BR is recognized. ...

Page 32

... ADSP-216x TIMING PARAMETERS (ADSP-2162/ADSP-2164/ADSP-2166) MEMORY READ Parameter Timing Requirements: RD Low to Data Valid t RDD A0–A13, PMS, DMS, BMS Data Valid Data Hold from RD High t RDH Switching Characteristics: RD Pulsewidth t RP CLKOUT High to RD Low t CRD A0–A13, PMS, DMS, BMS t ASR Setup Before RD Low A0– ...

Page 33

... TIMING PARAMETERS (ADSP-2162/ADSP-2164/ADSP-2166) MEMORY WRITE Parameter Switching Characteristics: Data Setup Before WR High t DW Data Hold After WR High Pulsewidth Low to Data Enabled t WDE A0–A13, DMS, DMS Setup t ASW Before WR Low Data Disable Before WR t DDR or RD Low CLKOUT High to WR Low ...

Page 34

... ADSP-216x TIMING PARAMETERS (ADSP-2162/ADSP-2164/ADSP-2166) SERIAL PORTS Parameter Timing Requirements: t SCLK Period SCK t DR/TFS/RFS Setup SCS Before SCLK Low t DR/TFS/RFS Hold After SCH SCLK Low t SCLK Width SCP IN Switching Characteristics: t CLKOUT High to SCLK CC OUT t SCLK High to DT Enable SCDE t SCLK High to DT Valid ...

Page 35

... IRQ2 36 RESET GND A10 51 A11 –35– ADSP-216x SCLK1 IRQ0 IRQ1 SCLK0 DR0 50 49 GND RFS0 48 TFS0 47 DT0 ...

Page 36

... PMS 12 32 DMS 13 33 BMS XTAL 36 17 CLKIN 37 18 PWDACK PWDFLAG *ADSP-2165/ADSP-2166 only. Others “NC”. PIN CONFIGURATIONS 80-Lead MQFP 1 PIN 1 2 IDENTIFIER ADSP-216x 10 TOP VIEW 11 (Not to Scale ...

Page 37

... IDENTIFIER TOP VIEW (PINS DOWN 0.954 (24.23) 0.950 (24.13) REV. 0 OUTLINE DIMENSIONS ADSP-216x 68-Lead Plastic Leaded Chip Carrier (PLCC) 0.175 (4.45) 0.169 (4.29 0.050 (1.27) TYP 0.925 (23.50) 0.895 (22.73) 0.019 (0.48) 0.017 (0.43) 0.029 (0.74) 0.027 (0.69 0.104 (2.64) TYP –37– ADSP-216x PIN 1 IDENTIFIER BOTTOM VIEW (PINS UP) ...

Page 38

... ADSP-216x 0.041 (1.03) 0.031 (0.78) OUTLINE DIMENSIONS ADSP-216x 80-Lead Plastic Quad Flatpack (MQFP) 0.690 (17.45) 0.667 (16.95) 0.134 (3.40) 0.555 (14.10) MAX 0.547 (13.90) 0.486 (12.35) BSC 80 1 SEATING PLANE TOP VIEW (PINS DOWN) 0.004 (0.10 MAX 0.010 (0.25) 0.014 (0.35) MIN 0.026 (0.65) BSC 0.120 (3.05) 0.010 (0.25) 0.100 (2.55) THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0 ...

Page 39

... ADSP-2163BP-100 2 ADSP-2163KS-100 2 ADSP-2163BS-100 2 ADSP-2164KP-40 (3 ADSP-2164BP-40 (3 ADSP-2164KS-40 (3 ADSP-2164BS-40 (3.3 V) ADSP-2165KS-80 ADSP-2165KS-100 ADSP-2165BS-80 ADSP-2165BS-100 ADSP-2166KS-52 (3.3 V) ADSP-2166KS-66 (3.3 V) ADSP-2166BS-52 (3.3 V) ADSP-2166BS-66 (3.3 V) NOTES Commercial Temperature Range ( +70 C Industrial Temperature Range (– +85 C PLCC (Plastic Leaded Chip Carrier MQFP (Plastic Quad Flatpack). ...

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