adsp-21483 Analog Devices, Inc., adsp-21483 Datasheet

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... Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. ADSP-21483/21486/21487/21488/21489 Qualified for Automotive Applications. See Products on Page 64 Code compatible with all other members of the SHARC family ...

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... ADSP-21483/21486/21487/21488/21489 TABLE OF CONTENTS Summary ............................................................... 1 Table Of Contents .................................................... 2 Revision History ...................................................... 2 General Description ................................................. 3 Family Core Architecture ........................................ 4 Family Peripheral Architecture ................................ 6 I/O Processor Features ......................................... 11 System Design .................................................... 12 Development Tools ............................................. 12 Additional Information ........................................ 13 Pin Function Descriptions ....................................... 14 Specifications ........................................................ 18 Operating Conditions .......................................... 18 Electrical Characteristics ....................................... 19 Package Information ........................................... 20 ESD Sensitivity ................................................... 20 Maximum Power Dissipation ................................ 20 Absolute Maximum Ratings .................................. 20 Timing Specifications ...

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... These products contain the Digital Transmission Content Protection protocol, a proprietary security protocol. Contact your Analog Devices sales office for more information. 3 The 100-lead packages of the ADSP-21483/21486/21488/ADSP-21489 processors do not contain an external port. And the ADSP-21486 processor in the 176-lead package does not contain a SDRAM controller. ...

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... ADSP-21483/21486/21487/21488/21489 The diagram on Page 1 shows the two clock domains that make up the ADSP-2148x processors. The core clock domain contains the following features. • Two processing elements (PEx, PEy), each of which com- prises an ALU, multiplier, shifter, and data register file • Data address generators (DAG1, DAG2) • ...

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... FFT butterfly processing. ADSP-21483/21486/21487/21488/21489 The data bus exchange register (PX) permits data to be passed between the 64-bit PM data bus and the 64-bit DM data bus, or between the 40-bit register file and the PM data bus. These reg- isters contain hardware to handle the data width difference ...

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... Source modules need to be built using the VISA option, in order to allow code genera- tion tools to create these more efficient opcodes. On-Chip Memory The ADSP-21483 and the ADSP-21488 processors contain 3 Mbits of internal RAM (Table 3) and the ADSP-21486, ADSP-21487, and ADSP-21489 processors contain 5 Mbits of ...

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... Preliminary Technical Data Table 3. Internal Memory Space (ADSP-21483/ADSP-21488) Extended Precision Normal or Long Word (64 Bits) Instruction Word (48 Bits) Block 0 ROM (Reserved) Block 0 ROM (Reserved) 0x0004 0000–0x0004 7FFF 0x0008 0000–0x0008 AAA9 Reserved Reserved 0x0004 8000–0x0004 8FFF 0x0008 AAAA–0x0008 BFFF ...

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... ADSP-21483/21486/21487/21488/21489 Table 4. Internal Memory Space (ADSP-21486/ADSP-21487/ADSP-21489) Extended Precision Normal or Long Word (64 Bits) Instruction Word (48 Bits) Block 0 ROM (Reserved) Block 0 ROM (Reserved) 0x0004 0000–0x0004 7FFF 0x0008 0000–0x0008 AAA9 Reserved Reserved 0x0004 8000–0x0004 8FFF 0x0008 AAAA–0x0008 BFFF Block 0 SRAM Block 0 SRAM 0x0004 9000– ...

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... ADSP-21483/21486/21487/21488/21489 External Port Throughput The throughput for the external port, based on 166 MHz clock and 16-bit data bus, is 111 M bytes/s for the AMI and 333 M bytes/s for SDRAM ...

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... ADSP-21483/21486/21487/21488/21489 The DAI also includes eight serial ports, four precision clock generators (PCG), a S/PDIF transceiver, four ASRCs, and an input data port (IDP). The IDP provides an additional input path to the SHARC core, configurable as either eight channels of serial data single 20-bit wide synchronous parallel data acquisition port. Each data channel has its own DMA channel that is independent from the processor’ ...

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... Pulse waveform generation mode • Pulse width count/capture mode • External event watch dog mode ADSP-21483/21486/21487/21488/21489 The core timer can be configured to use FLAG3 as a timer expired signal, and the general-purpose timers have one bidirec- tional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register ...

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... ADSP-21483/21486/21487/21488/21489 Delay Line DMA The ADSP-2148x processor provides delay line DMA function- ality. This allows processor reads and writes to external delay line buffers (and hence to external memory) with limited core interaction. Scatter/Gather DMA The ADSP-2148x processor provides scatter/gather DMA func- tionality. This allows processor DMA reads/writes to/from non- contingeous memory blocks ...

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... EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)—use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support. ADSP-21483/21486/21487/21488/21489 Evaluation Kit ® board Analog Devices offers a range of EZ-KIT Lite ...

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... ADSP-21483/21486/21487/21488/21489 PIN FUNCTION DESCRIPTIONS Note that the 100 pin package does not support the external port. This includes ADDR, DATA, Memory Selects, AMI and SDRAM Control signals. Table 9. Pin Descriptions State During/ Name Type After Reset ADDR I/O/T (ipu) High-Z/ 23–0 driven low ...

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... In this table, all pins are LVTTL compliant with the exception of the thermal diode pins. Not all pins are available in the 100-lead LQFP package. For more information, see ADSP-21483/21486/21487/21488/21489 Description SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other SDRAM command pins, defines the operation for the SDRAM to perform. SDRAM Column Address Select. Connect to SDRAM’ ...

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... ADSP-21483/21486/21487/21488/21489 Table 9. Pin Descriptions (Continued) State During/ Name Type After Reset 1 MLBCLK I 3 MLBDAT I/O High-Z pin mode pin mode. 3 MLBSIG I/O High-Z pin mode pin mode 3 MLBDO O/T High-Z 3 MLBSO O/T High-Z TDI I (ipu) TDO O/T High-Z TMS I (ipu) TCK I TRST ...

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... The exposed pad is required to be electrically and thermally connected to GND. Implement this by soldering the exposed pad to a GND PCB land that is the same size as the exposed pad. The GND PCB land should be robustly connected to the GND plane in the PCB for best electrical and thermal performance. No separate GND pins are provided in the package. ADSP-21483/21486/21487/21488/21489 Description Core to CLKIN Ratio Control. These pins set the start up clock frequency. ...

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... ADSP-21483/21486/21487/21488/21489 SPECIFICATIONS OPERATING CONDITIONS 1 Parameter Description 2 V Internal (Core) Supply Voltage _ DD INT V External (I/O) Supply Voltage _ DD EXT V Thermal Diode Supply Voltage 3. THD 3 V High Level Input Voltage @ Max _ DD EXT 4 V Low Level Input Voltage @ Min _ DD ...

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... Applies to three-statable pins with pull-ups: DAI_Px, DPI_Px, EMU. 8 Typical internal current data reflects nominal operating conditions. 9 See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-2148x SHARC Processors” for further information. 10 Applies to all signal pins. 11 Guaranteed, but not tested. ADSP-21483/21486/21487/21488/21489 300 MHz Min Typical Max Min = Min, 3 2.4 2.4 = Min, 0 ...

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... ADSP-21483/21486/21487/21488/21489 PACKAGE INFORMATION The information presented in Figure 3 the package branding for the ADSP-2148x processors. For a complete listing of product availability, see Page 65. ADSP-2148x tppZ-cc vvvvvv.x n.n #yyww country_of_origin Figure 3. Typical Package Brand Table 11. Package Brand Information Brand Key Field Description t Temperature Range pp Package Type ...

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... CLKIN DIVIDER XTAL BUF PMCTL (INDIV) DELAY OF 4096 CLKIN CYCLES ADSP-21483/21486/21487/21488/21489 f INPUT f INPUT Note the definitions of the clock periods that are a function of CLKIN and the appropriate ratio control shown in and Table 13. All of the timing specifications for the ADSP-2148x peripherals are defined in relation to t specific section for each peripheral’ ...

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... ADSP-21483/21486/21487/21488/21489 Power-Up Sequencing The timing requirements for processor startup are given in Table 14. While no specific power-up sequencing is required between V and V , there are some considerations that EXT DD INT system designs should take into account. • No power supply should be powered up for an extended period of time (> 200 ms) before another supply starts to ramp up. • ...

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... The ADSP-2148x can use an external clock or a crystal. See the CLKIN pin description in Table 9 on Page configure the processor to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. Figure 7 shows the component connections used for a crystal CLKIN C1 22pF *TYPICAL VALUES ADSP-21483/21486/21487/21488/21489 350 MHz Min 1 22 2.85 200 –250 t ...

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... ADSP-21483/21486/21487/21488/21489 Reset Table 16. Reset Parameter Timing Requirements 1 t RESET Pulse Width Low WRST t RESET Setup Before CLKIN Low SRST Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable ...

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... IPW Core Timer The following timing specification applies to FLAG3 when it is configured as the core timer (TMREXP). Table 19. Core Timer Parameter Switching Characteristic t TMREXP Pulse Width WCTIM FLAG3 (TMREXP) ADSP-21483/21486/21487/21488/21489 DAI_P20–1 DPI_P14–1 FLAG2– IPW Figure 10. Interrupts Min 4 × t – 1 ...

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... ADSP-21483/21486/21487/21488/21489 Timer PWM_OUT Cycle Timing The following timing specification applies to timer0 and timer1 in PWM_OUT (pulse-width modulation) mode. Timer signals are routed to the DPI_P14–1 pins through the DPI SRU. There- fore, the timing specifications provided below are valid at the DPI_P14–1 pins. ...

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... WDT_CLKO Pin to Pin Direct Routing (DAI and DPI) For direct pin connections only (for example DAI_PB01_I to DAI_PB02_O). Table 23. DAI/DPI Pin to Pin Routing Parameter Timing Requirement t Delay DAI/DPI Pin Input Valid to DAI/DPI Output Valid DPIO ADSP-21483/21486/21487/21488/21489 Min 3.7059 64 × t WDTCLKPER t WDTCLKPER t RST t RSTPW Figure 14 ...

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... ADSP-21483/21486/21487/21488/21489 Precision Clock Generator (Direct Pin Routing) This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other cases, where the PCG’s Table 24 ...

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... FLAGs IN Pulse Width FIPW Switching Characteristic t FLAGs OUT Pulse Width FOPW 1 This is applicable when the Flags are connected to DPI_P14–1, ADDR7–0, DATA7–0 and FLAG3–0 pins. (FLAG3–0 (FLAG3–0 ADSP-21483/21486/21487/21488/21489 Table DPI_14– (DATA7–0) (ADDR7–0) t DPI_14– ...

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... ADSP-21483/21486/21487/21488/21489 SDRAM Interface Timing (166 MHz SDCLK) The processor needs to be programmed in t mode when operated at 400 MHz. 1 Table 26. SDRAM Interface Timing Parameter Timing Requirements t DATA Setup Before SDCLK SSDAT t DATA Hold After SDCLK HSDAT Switching Characteristics t SDCLK Period SDCLK t SDCLK Width High ...

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... SDCLK Disable After CLKIN Rise DSDCC t SDCLK Enable After CLKIN Rise ENSDCC t Address Disable After CLKIN Rise DSDCA t Address Enable After CLKIN Rise ENSDCA 1 For f = 400 MHz (core clock to SDCLK ratio = 1:2.5). CCLK ADSP-21483/21486/21487/21488/21489 1 CLKIN t DSDC t DSDCC t DSDCA COMMAND SDCLK ADDR t ENSDC t ...

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... ADSP-21483/21486/21487/21488/21489 Memory Read—Bus Master Use these specifications for asynchronous interfacing to memo- ries. Note that timing for AMI_ACK, ADDR, DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asyn- chronous access mode. Table 28. Memory Read—Bus Master Parameter Timing Requirements t Address, Selects Delay to Data Valid ...

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... Preliminary Technical Data ADDR t DARL DATA t AMI_ACK ADSP-21483/21486/21487/21488/21489 DRLD t DAD t DSAK DAAK Figure 20. Memory Read—Bus Master Rev. PrA | Page March 2010 t DRHA t SDS t HDRH t RWR ...

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... ADSP-21483/21486/21487/21488/21489 Memory Write—Bus Master Use these specifications for asynchronous interfacing to memo- ries. Note that timing for AMI_ACK, ADDR, DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asyn- chronous access mode. Table 29. Memory Write—Bus Master Parameter Timing Requirements t AMI_ACK Delay from Address, Selects ...

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... Transmit or Receive SCLK Width SCKLIW 1 Referenced to the sample edge. 2 Referenced to drive edge. ADSP-21483/21486/21487/21488/21489 Serial port signals (SCLK, FS, Data Channel A, Data Channel B) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Min 2 ...

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... ADSP-21483/21486/21487/21488/21489 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE t SCLKIW DAI_P20–1 (SCLK) t DFSIR t t HOFSIR SFSI DAI_P20–1 (FRAME SYNC) t SDRI DAI_P20–1 (DATA CHANNEL A/B) NOTES 1. EITHER THE RISING EDGE OR THE FALLING EDGE OF SCLK (EXTERNAL OR INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. ...

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... USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20–1 PINS. THE CHARACTERIZED SPORT AC TIMINGS ARE APPLICABLE WHEN INTERNAL CLOCKS AND FRAMES ARE LOOPED BACK FROM THE PIN, NOT ROUTED DIRECTLY THROUGH THE SRU. 1 This figure reflects changes made to support left-justified mode. ADSP-21483/21486/21487/21488/21489 EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0 SAMPLE DRIVE t ...

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... ADSP-21483/21486/21487/21488/21489 Table 33. Serial Ports—Enable and Three-State Parameter Switching Characteristics 1 t Data Enable from External Transmit SCLK DDTEN 1 t Data Disable from External Transmit SCLK DDTTE 1 t Data Enable from Internal Transmit SCLK DDTIN 1 Referenced to drive edge. DRIVE EDGE DAI_P20–1 (SCLK, EXT) DAI_P20– ...

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... The serial clock, data and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins. DAI_P20–1 (SERIAL CLOCK) DAI_P20–1 (FRAME SYNC) DAI_P20–1 (DATA) ADSP-21483/21486/21487/21488/21489 Table 34. IDP Min 4 2.5 2.5 2.5 (t × ...

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... ADSP-21483/21486/21487/21488/21489 Parallel Data Acquisition Port (PDAP) The timing requirements for the PDAP are provided in Table 35. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the PDAP, see the Table 35. Parallel Data Acquisition Port (PDAP) Parameter Timing Requirements ...

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... The serial clock, data and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. DAI_P20–1 (SERIAL CLOCK) DAI_P20–1 (FRAME SYNC) DAI_P20–1 (DATA) ADSP-21483/21486/21487/21488/21489 Min 4 5.5 4 5.5 (t PCLK ...

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... ADSP-21483/21486/21487/21488/21489 Sample Rate Converter—Serial Output Port For the serial output port, the frame-sync is an input and it should meet setup and hold times with regard to SCLK on the output port. The serial data output has a hold time and delay Table 37. ASRC, Serial Output Port ...

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... The following timing specifications apply when the ADDR23–8/DPI_14–1 pins are configured as PWM. Table 38. Pulse-Width Modulation (PWM) Timing Parameter Switching Characteristics t PWM Output Pulse Width PWMW t PWM Output Period PWMP PWM OUTPUTS ADSP-21483/21486/21487/21488/21489 Min t – 2 PCLK 2 × t – 1.5 PCLK t PWMW t PWMP Figure 29. PWM Timing Rev ...

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... ADSP-21483/21486/21487/21488/21489 S/PDIF Transmitter Serial data input to the S/PDIF transmitter can be formatted as 2 left justified right justified with word widths of 16-, 18-, 20-, or 24-bits. The following sections provide timing for the transmitter. S/PDIF Transmitter-Serial Input Waveforms Figure 30 shows the right-justified mode. LRCLK is high for the left channel and low for the right channel ...

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... The S/PDIF transmitter has an oversampling clock. This HFCLK input is divided down to generate the biphase clock. Table 40. Over Sampling Clock (HFCLK) Switching Characteristics Parameter HFCLK Frequency for HFCLK = 384 × Frame Sync HFCLK Frequency for HFCLK = 256 × Frame Sync Frame Rate (FS) ADSP-21483/21486/21487/21488/21489 SAMPLE EDGE t t SITXCLKW SITXCLK t ...

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... ADSP-21483/21486/21487/21488/21489 S/PDIF Receiver The following section describes timing as it relates to the S/PDIF receiver. Internal Digital PLL Mode In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the 512 × FS clock. Table 41. S/PDIF Receiver Internal Digital PLL Mode Timing ...

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... SPICLM SPICLK ( (OUTPUT) MOSI (OUTPUT) CPHASE = 1 MISO (INPUT) MOSI MSB (OUTPUT SSPIDM HSPIDM CPHASE = 0 MISO MSB VALID (INPUT) ADSP-21483/21486/21487/21488/21489 t SPICLM t SPICHM t HDSPIDM t DDSPIDM MSB t SSPIDM t HSPIDM MSB VALID t DDSPIDM LSB VALID Figure 35. SPI Master Timing Rev. PrA | Page March 2010 ...

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... ADSP-21483/21486/21487/21488/21489 SPI Interface—Slave Table 43. SPI Interface Protocol—Slave Switching and Timing Specifications Parameter Timing Requirements t Serial Clock Cycle SPICLKS t Serial Clock High Period SPICHS t Serial Clock Low Period SPICLS t SPIDS Assertion to First SPICLK Edge SDSCO CPHASE = 0 CPHASE = 1 t Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 ...

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... DDSPIDS t DSOE MISO (OUTPUT) t CPHASE = 1 SSPIDS MOSI (INPUT) MISO MSB (OUTPUT) t DSOV CPHASE = 0 MOSI MSB VALID (INPUT) ADSP-21483/21486/21487/21488/21489 t t SPICLS SPICLKS t SPICHS t DDSPIDS MSB MSB VALID t DDSPIDS LSB t SSPIDS LSB VALID Figure 36. SPI Slave Timing Rev. PrA | Page March 2010 ...

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... ADSP-21483/21486/21487/21488/21489 Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing Figure 37 describes UART port receive and transmit operations. The maximum baud rate is PCLK/16 where PCLK = 1/tPCLK. As shown in Figure 37 there is some latency between the gener- Table 44. UART Port Parameter Timing Requirement 1 t Incoming Data Pulse Width ...

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... Bus Free Time Between a Stop and Start Condition BUF t Pulse Width of Spikes Suppressed By the Input Filter SP 1 All values referred to V and V levels. For more information, see Electrical Characteristics on page 19. IHmin ILmax DPI_P14–1 SDA DPI_P14–1 SCL S ADSP-21483/21486/21487/21488/21489 Standard Mode Min 0 4.0 4.7 4.0 4.7 0 250 4.0 4.7 n SUDAT ...

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... ADSP-21483/21486/21487/21488/21489 Media Local Bus All the numbers given are applicable for all speed modes (1024Fs, 512Fs and 256Fs for 3-pin; 512Fs and 256Fs for 5-pin) unless otherwise specified. Please refer to the MediaLB specifi- cation document rev 3.0 for more details. Table 46. MLB Interface, 3-pin Specifications ...

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... When a node is not driving valid data onto the bus, the MLBSO and MLBDO output lines shall remain low. If the output lines can float at anytime, including while in reset, external pull-down resistors are required to keep the outputs from corrupting the MediaLB signal lines when not being driven. ADSP-21483/21486/21487/21488/21489 VALID ...

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... ADSP-21483/21486/21487/21488/21489 MLBSIG/ MLBDAT (Rx, Input) MLBCLK MLBSO/ MLBDO (Tx, Output) VALID t DHMCF t DSMCF t MCKH t MCKL t MCKR t MCKF t MLBCLK t MCDRV VALID Figure 40. MLB Timing (5-Pin Interface) MLBCLK t t MPWV MPWV Figure 41. MLB 3-Pin and 5-Pin MLBCLK Pulse Width Variation Timing Rev. PrA | Page March 2010 ...

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... System Outputs = DAI_Px, DPI_Px ADDR23–0, AMI_RD, AMI_WR, FLAG3–0, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDDQM, SDCLK, MLBDAT, MLBSIG, MLBDO, MLBSO, and EMU. TCK TMS TDI t DTDO TDO SYSTEM INPUTS SYSTEM OUTPUTS ADSP-21483/21486/21487/21488/21489 t TCK t t STAP HTAP t t SSYS HSYS t DSYS Figure 42 ...

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... ADSP-21483/21486/21487/21488/21489 OUTPUT DRIVE CURRENTS Figure 43 shows typical I-V characteristics for the output driv- ers of the ADSP-2148x. The curves represent the current drive capability of the output drivers as a function of output voltage TBD 100 150 Figure 43. Typical Drive at Junction Temperature ...

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... T A Values of θ are provided for package comparison and PCB JC design considerations when an external heatsink is required. ADSP-21483/21486/21487/21488/21489 Values of θ design considerations. Note that the thermal characteristics val- ues provided in Table 49. Thermal Characteristics for 100-Lead LQFP_EP Parameter θ JA θ ...

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... ADSP-21483/21486/21487/21488/21489 Table 51 contains the thermal diode specifications using the transistor model. Table 51. Thermal Diode Parameters – Transistor Model Symbol Parameter 1 I Forward Bias Current FW I Emitter Current Transistor Ideality Series Resistance T 1 Analog Devices does not recommend operation of the thermal diode under reverse bias. ...

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... INT RESETOUT/RUNRSTIN INT DPI_P01 19 DPI_P02 20 DPI_P03 INT DPI_P05 23 DPI_P04 24 DPI_P06 25 * Pin no. 101 is the GND supply (see Figure 49 ADSP-21483/21486/21487/21488/21489 Pin Name Pin No. Pin Name V 26 DAI_P10 _ DD EXT DPI_P08 DPI_P07 DAI_P20 _ DD INT DPI_P09 ...

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... ADSP-21483/21486/21487/21488/21489 Figure 49 shows the top view of the 100-lead LQFP_EP pin con- figuration. Figure 50 shows the bottom view of the 100-lead LQFP_EP lead configuration. PIN 1 INDICATOR ADSP-2148x 100-LEAD LQFP_EP BOTTOM VIEW PIN 100 PIN 76 PIN 1 ADSP-2148x 100-LEAD LQFP_EP TOP VIEW PIN 25 PIN 26 PIN 50 Figure 49 ...

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... ADDR18 35 RESETOUT/RUNRSTIN INT DPI_P01 38 DPI_P02 39 DPI_P03 INT DPI_P05 42 DPI_P04 43 DPI_P06 44 * Pin no. 177 is the GND supply (see Figure 51 ADSP-21483/21486/21487/21488/21489 Pin Name Pin No. Pin Name V 45 DAI_P10 _ DD EXT DPI_P08 DPI_P07 DAI_P20 _ DD INT DPI_P09 ...

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... ADSP-21483/21486/21487/21488/21489 Figure 51 shows the top view of the 176-lead LQFP_EP pin con- figuration. Figure 52 shows the bottom view of the 176-lead LQFP_EP lead configuration. PIN 1 INDICATOR ADSP-2148x 176-LEAD LQFP_EP BOTTOM VIEW PIN 176 PIN 133 PIN 1 ADSP-2148x 176-LEAD LQFP_EP TOP VIEW PIN 44 PIN 45 PIN 88 Figure 51 ...

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... The ADSP-2148x processors are available in a 100-lead and 176-lead LQFP_EP RoHS compliant packages. 1.60 MAX 0.75 0.60 0.45 SEATING PLANE 1.45 0.20 1.40 0.15 1.35 0.09 0.15 7° 0.10 3.5° 0.05 0.08 0° COPLANARITY VIEW A ROTATED 90° CCW Figure 53. 100-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP] ADSP-21483/21486/21487/21488/21489 16.20 16.00 SQ 15.80 14.20 14.00 SQ 13.80 100 PIN 1 TOP VIEW (PINS DOWN 0.27 VIEW A 0.22 0.50 0.17 BSC ...

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... ADSP-21483/21486/21487/21488/21489 1.60 MAX 0.75 0.60 0.45 1.00 REF SEATING PLANE 1.45 0.20 1.40 0.15 1.35 0.09 0.15 7° 0.10 3.5° 0.05 0.08 0° COPLANARITY VIEW A ROTATED 90° CCW SURFACE-MOUNT DESIGN The exposed pad is required to be electrically and thermally connected to GND. Implement this by soldering the exposed pad to a GND PCB land that is the same size as the exposed pad. ...

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... Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see specification which is the only temperature specification. 3 Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at www.analog.com/SHARC ADSP-21483/21486/21487/21488/21489 Processor Instruction 2 RAM ...

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... ADSP-21483/21486/21487/21488/21489 ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR09018-0-3/10(PrA) Rev. PrA | Page March 2010 Preliminary Technical Data ...