adsp-21469 Analog Devices, Inc., adsp-21469 Datasheet
adsp-21469
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adsp-21469 Summary of contents
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... Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Code compatible with all other members of the SHARC family The ADSP-21469 is available with a 450 MHz core instruction rate with unique audiocentric peripherals such as the digi- tal applications interface, serial ports, precision clock generators, S/PDIF transceiver, asynchronous sample rate converters, input data port, and more ...
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... FIR accelerators perform dedicated FIR filtering with high- performance, fixed- and floating-point processing capabil- ities with no core intervention In the ADSP-21469, the program sequencer can execute code directly from external memory bank 0 (SRAM, as well as DDR2 DRAM). This allows more options to a user in terms of code and data storage ...
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... Maximum Power Dissipation ................................. 18 Absolute Maximum Ratings ................................... 18 ESD Sensitivity .................................................... 18 Timing Specifications ........................................... 19 Output Drive Currents .......................................... 50 Test Conditions ................................................... 50 Capacitive Loading ............................................... 50 Thermal Characteristics ........................................ 51 Ball configuration - ADSP-21469 ............................. 52 PBGA Pinout ......................................................... 53 Outline Dimensions ................................................ 55 Automotive Products ............................................... 56 Ordering Guide ...................................................... 56 REVISION HISTORY 11/08—Revision PrB Rev. PrB | Page November 2008 ADSP-21469/ADSP-21469W ...
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... SPI TWI Package As shown in the functional block diagram ADSP-21469 uses two computational units to deliver a signifi- cant performance increase over the previous SHARC processors on a range of DSP algorithms. Fabricated in a state-of-the-art, high speed, CMOS process, the ADSP-21469 processor achieves an instruction cycle time of 2. 450 MHz. With its SIMD computational hardware, the ADSP-21469 can perform 2 ...
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... Flexible Instruction Set The 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the ADSP-21469 can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetch- ing up to four 32-bit values from memory—all in a single instruction ...
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... Reserved 0x0007 4000–0x0007 FFFF 0x000E 8000–0x000F FFFF The ADSP-21469’s SRAM can be configured as a maximum of 160k words of 32-bit data, 320k words of 16-bit data, 106.7k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes megabit. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words ...
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... DDR2 space is different for VISA and non-VISA mode. DDR2 Support The ADSP-21469 supports a 16-bit DDR interface operating at a maximum frequency of half the core clock. Execution from external memory is supported. External memory Gbits can be supported. Delay line DMA functionality supported. ...
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... S/PDIF transceiver, four ASRCs, and an input data port (IDP). The IDP provides an additional input path to the ADSP-21469 core, configurable as either eight chan- nels of serial data single 20-bit wide synchronous parallel data acquisition port. Each data channel has its own DMA channel that is independent from the ADSP-21469’ ...
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... In conjunction with the general-purpose timer functions, auto- baud detection is supported. Timers The ADSP-21469 has a total of three timers: a core timer that can generate periodic software interrupts and two general pur- pose timers that can generate periodic interrupts and be independently set to operate in one of three modes: • ...
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... Target Board JTAG Emulator Connector Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-21469 pro- cessor to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG ...
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... EZ-KIT Lite board enables high speed, non- intrusive emulation. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-21469 architecture and functionality. For detailed information on the ADSP-21469 family core architecture and instruction set, refer to the ADSP-2136x/ADSP-2146x SHARC Processor Program- ming Reference ...
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... High-Z AMI Port Read Enable. AMI_RD is asserted whenever the ADSP-21469 reads a word from external memory. AMI_RD has fixed internal pull-up resistor High-Z External Port Write Enable. AMI_WR is asserted when the ADSP-21469 writes a word to external memory ...
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... Test Data Output (JTAG). Serial scan output of the boundary scan path. Test Mode Select (JTAG). Used to control the test state machine. TMS has a fixed internal pull-up resistor Rev. PrB | Page November 2008 ADSP-21469/ADSP-21469W are decoded emory address lines. Each DDR2_CS 3 ...
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... Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal. Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21469 clock input. It configures the ADSP-21469 to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator ...
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... Table 9. Core Instruction Rate/ CLKIN Ratio Selection CLKCFG1–0 Core to CLKIN Ratio 00 6:1 01 32:1 11 Reserved 10 16:1 provides the pin AMI_ADDR [23:8] AMI_ADDR [7:0] AMI_ADDR [23:0] Reserved Reserved FLAGS/PWM [15–0] Reserved PDAP (DATA + CTRL) Reserved Three-state all pins and Rev. PrB | Page November 2008 ADSP-21469/ADSP-21469W AMI_DATA [7:0] AMI_DATA [7:0] FLAGS [15–0] FLAGS [7–0] ...
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... ADSP-21469/ADSP-21469W SPECIFICATIONS OPERATING CONDITIONS 1 Parameter Description V Internal (Core) Supply Voltage DD_INT V External (I/O) Supply Voltage DD_EXT 3 V DDR2 Controller Supply Voltage DD_DDR2 V DDR2 Reference Voltage REF 4 V High Level Input Voltage @ Low Level Input Voltage @ High Level Input Voltage @ V ...
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... Applies to three-statable pins with 22.5 k pull-ups: DAI_Px, DPI_Px, EMU. 9 Typical internal current data reflects nominal operating conditions. 10 See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-21469 SHARC Processors” for further information. 11 Applies to all signal pins. 12 Guaranteed, but not tested. Test Conditions ...
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... ADSP-21469/ADSP-21469W MAXIMUM POWER DISSIPATION See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-21469 SHARC Processors” for detailed thermal and power information regarding maximum power dissipation. For information on package thermal specifications, see Characteristics on Page 51. ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in Table 10 nent damage to the device. These are stress ratings only ...
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... Preliminary Technical Data TIMING SPECIFICATIONS The ADSP-21469’s internal clock (a multiple of CLKIN) pro- vides the clock signal for timing internal memory, processor core, and serial ports. During reset, program the ratio between the processor’s internal clock frequency and external (CLKIN) clock frequency with the CLKCFG1– ...
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... ADSP-21469/ADSP-21469W Table 12. Clock Periods Timing 1 Requirements Description t CLKIN Clock Period CK t (Processor) Core Clock Period CCLK t (Link Port) Core Clock Period LCLK t (Peripheral) Clock Period = 2 × t PCLK t Serial Port Clock Period = (t SCLK t DDR2 DRAM Clock Period = (t DDR2_CLK t SPI Clock Period = (t SPICLK ...
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... _IVD Figure 4. Power-Up Sequencing Rev. PrB | Page November 2008 ADSP-21469/ADSP-21469W Min Max 0 TBD TBD 0 200 4096 t ...
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... CK CLKIN t CKH Figure 5. Clock Input Clock Signals The ADSP-21469 can use an external clock or a crystal. See the CLKIN pin description in Table 6. The programmer can config- ure the ADSP-21469 to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. Figure 6 shows the component connections used for a crystal operating in fundamental mode ...
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... Running RESET Setup Before CLKIN High SRUNRST CLKIN RUNRSTIN Min TBD TBD t WRST Figure 7. Reset Min TBD TBD t SRUNRST t WRUNRST Figure 8. Running Reset Rev. PrB | Page November 2008 ADSP-21469/ADSP-21469W Max Unit TBD ns TBD ns while RESET is low, assuming stable t SRST Max Unit TBD ns TBD ns ...
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... ADSP-21469/ADSP-21469W Interrupts The following timing specification applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0, IRQ1, and IRQ2 interrupts as well as the DAI_P20-1 and DPI_P14-1 pins when they are configured as interrupts. Table 17. Interrupts Parameter Timing Requirement t IRQx Pulse Width ...
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... Delay DAI/DPI Pin Input Valid to DAI Output Valid DPIO Min TBD t PWI Figure 12. Timer Width Capture Timing Min TBD DAI_Pn DPI_Pn DAI_Pm DPI_Pm t DPIO Figure 13. DAI Pin to Pin Direct Routing Rev. PrB | Page November 2008 ADSP-21469/ADSP-21469W Max Unit TBD ns Max Unit TBD ns ...
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... ADSP-21469/ADSP-21469W Precision Clock Generator (Direct Pin Routing) This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other cases, where the PCG’s Table 22 ...
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... Switching Characteristic t DPI_P14-1, AMI_ADDR23-0, AMI_DATA7-0, FLAG3–0 OUT Pulse Width TBD FOPW DPI_P14 (FLAG3 (AMI_DATA7 (AMI_ADDR23-0) DPI_P14 (FLAG3 (AMI_DATA7 AMI_ADDR23- FIPW - OUT - 0) t FOPW Figure 15. Flags Rev. PrB | Page November 2008 ADSP-21469/ADSP-21469W Min Max TBD TBD Unit ns ns ...
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... ADSP-21469/ADSP-21469W DDR2 SDRAM Read Cycle Timing Table 24. DDR2 SDRAM Read Cycle Timing, V Parameter Symbol Timing Requirements TBD TBD TBD nominal 1.8V DD-DDR2 Figure 16. DDR2 SDRAM Controller Input AC Timing Rev. PrB | Page November 2008 Preliminary Technical Data Minimum Maximum Unit TBD TBD ...
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... Preliminary Technical Data DDR2 SDRAM Write Cycle Timing Table 25. DDR2 SDRAM Write Cycle Timing, V Parameter Symbol Switching Characteristics TBD TBD TBD nominal 1.8V DD-DDR2 Figure 17. DDR2 SDRAM Controller Output AC Timing Rev. PrB | Page November 2008 ADSP-21469/ADSP-21469W Minimum Maximum Unit TBD TBD TBD ...
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... ADSP-21469/ADSP-21469W Memory Read—Bus Master Use these specifications for asynchronous interfacing to memo- ries. Note that timing for AMI_ACK, AMI_DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asyn- chronous access mode. Table 26. Memory Read—Bus Master Parameter Timing Requirements t Address, Selects Delay to Data Valid ...
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... for deassertion of AMI_ACK (low). For asynchronous assertion of AMI_ACK (high) user must meet t DSAK t DAWH WDE t DDWH t DSAK Figure 19. Memory Write—Bus Master Rev. PrB | Page November 2008 ADSP-21469/ADSP-21469W Max Unit TBD ns TBD ns TBD TBD ns TBD ns TBD ns TBD ns TBD ...
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... ADSP-21469 Setup Skew = TBD ns max LCLK- ADSP-21469 Hold Skew = TBD ns max Note that there is a two-cycle effect latency between the link port enable instruction and the DSP enabling the link port. Min ...
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... Min TBD TBD TBD TBD TBD TBD TBD TBD LAST BYTE FIRST BYTE TRANSMITTED TRANSMITTED t t SLACH HLACH Figure 21. Link Ports—Transmit Rev. PrB | Page November 2008 ADSP-21469/ADSP-21469W Max Unit TBD ns TBD ns TBD TBD ns TBD ns TBD ns TBD ns TBD ns LCLK INACTIVE ...
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... ADSP-21469/ADSP-21469W Serial Ports To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width. Table 30. Serial Ports—External Clock ...
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... SFSE/I HFSE/I t DDTE/I t DDTENFS t HDTE/I 1ST BIT t DDTLFSE DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20 1 Figure 22. External Late Frame Sync Rev. PrB | Page November 2008 ADSP-21469/ADSP-21469W Max Unit TBD ns TBD ns TBD ns Max Unit TBD ns TBD ns t DDTE/I 2ND BIT 2ND BIT ...
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... ADSP-21469/ADSP-21469W DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE t SCLKIW - DAI_P20 1 (SCLK) t DFSIR t HOFSIR - DAI_P20 1 (FS) - DAI_P20 1 (DATA CHANNEL A/B) NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL) OR SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE t SCLKIW ...
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... IDP SAMPLE EDGE t IPDCLK IPDCLKW t t SISFS SIHFS - 1 (FS SISD SIHD - 1 Figure 24. IDP Master Timing Rev. PrB | Page November 2008 ADSP-21469/ADSP-21469W Min Max Unit TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns TBD TBD ns Min Max ...
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... ADSP-21469/ADSP-21469W - DAI_P20 (SCLK) - DAI_P20 (FS) - DAI_P20 1 (SDATA) SAMPLE EDGE t SRCCLK t 1 SRCCLKW t t SRCSFS SRCHFS SRCSD Figure 25. ASRC Serial Input Port Timing Rev. PrB | Page November 2008 Preliminary Technical Data SRCHD ...
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... Min TBD TBD TBD TBD TBD TBD TBD SAMPLE EDGE t SRCCLK t SRCCLKW t t SRCSFS SRCHFS t SRCTDD t SRCTDH Figure 26. ASRC Serial Output Port Timing Rev. PrB | Page November 2008 ADSP-21469/ADSP-21469W Max Unit TBD ns TBD ns TBD ns TBD ns TBD TBD ns TBD ns ...
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... ADSP-21469/ADSP-21469W Parallel Data Acquisition Port (PDAP) The timing requirements for the PDAP are provided in Table 37. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the PDAP, see the PDAP chapter of the ADSP-2146x SHARC Processor Hardware Table 37. Parallel Data Acquisition Port (PDAP) ...
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... AMI_ADDR23-8 pins are configured as PWM. Table 38. Pulse-Width Modulation (PWM) Timing Parameter Switching Characteristics t PWM Output Pulse Width PWMW t PWM Output Period PWMP PWM OUTPUTS Min TBD TBD t PWMW t PWMP Figure 28. PWM Timing Rev. PrB | Page November 2008 ADSP-21469/ADSP-21469W Max Unit TBD ns TBD ns ...
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... ADSP-21469/ADSP-21469W S/PDIF Transmitter Serial data input to the S/PDIF transmitter can be formatted as 2 left justified right justified with word widths of 16-, 18-, 20-, or 24-bits. The following sections provide timing for the transmitter. S/PDIF Transmitter-Serial Input Waveforms Figure 29 shows the right-justified mode. LRCLK is high for the left channel and low for the right channel ...
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... TBD TBD TBD TBD TBD t SITXCLKW t SITXCLK t SISCLKW t SISCLK t SISFS t SISD Figure 32. S/PDIF Transmitter Input Timing Min TBD TBD TBD Rev. PrB | Page November 2008 ADSP-21469/ADSP-21469W Max Unit TBD ns TBD ns TBD ns TBD ns TBD ns TBD ns TBD ns TBD ns t SIHFS t SIHD Max ...
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... ADSP-21469/ADSP-21469W S/PDIF Receiver The following section describes timing as it relates to the S/PDIF receiver. Internal Digital PLL Mode In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the TBD × FS clock. Table 41. S/PDIF Receiver Internal Digital PLL Mode Timing ...
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... Preliminary Technical Data SPI Interface—Master The ADSP-21469 contains two SPI ports. Both primary and sec- ondary are available through DPI only. The timing provided in Table 42 and Table 43 applies to both. Table 42. SPI Interface Protocol—Master Switching and Timing Specifications Parameter Timing Requirements ...
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... ADSP-21469/ADSP-21469W SPI Interface—Slave Table 43. SPI Interface Protocol—Slave Switching and Timing Specifications Parameter Timing Requirements t Serial Clock Cycle SPICLKS t Serial Clock High Period SPICHS t Serial Clock Low Period SPICLS t SPIDS Assertion to First SPICLK Edge SDSCO CPHASE = 0 CPHASE = 1 t Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 ...
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... TBD - DATA(5 8) STOP tRXD - DATA(5 8) STOP(1 tTXD Figure 36. UART Port—Receive and Transmit Timing Rev. PrB | Page November 2008 ADSP-21469/ADSP-21469W Max Unit TBD ns TBD TBD ns UART RECEIVE BIT SET BY DATA STOP; CLEARED BY FIFO READ - 2) UART TRANSMIT BIT SET BY PROGRAM; CLEARED BY WRITE TO TRANSMIT ...
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... ADSP-21469/ADSP-21469W TWI Controller Timing Table 45 and Figure 37 provide timing information for the TWI interface. Input Signals (SCL, SDA) are routed to the DPI_P14–1 pins using the SRU. Therefore, the timing specifica- tions provided below are valid at the DPI_P14–1 pins. Table 45. Characteristics of the SDA and SCL Bus Lines for F/S-Mode TWI Bus Devices ...
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... TBD TBD TBD TBD TBD TBD TBD t TCK t t STAP HTAP t DTDO t t SSYS HSYS t DSYS Figure 38. IEEE 1149.1 JTAG Test Access Port Rev. PrB | Page November 2008 ADSP-21469/ADSP-21469W Max Unit TBD ns TBD ns TBD ns TBD ns TBD ns TBD ns TBD TBD ns TBD ns ...
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... ADSP-21469/ADSP-21469W OUTPUT DRIVE CURRENTS Figure 39 shows typical I-V characteristics for the output driv- ers of the ADSP-21469. The curves represent the current drive capability of the output drivers as a function of output voltage TBD 100 150 0 Figure 39. ADSP-21469 Typical Drive at Junction Temperature ...
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... Figure 44. Typical Output Delay or Hold vs. Load Capacitance (at Ambient Temperature) THERMAL CHARACTERISTICS The ADSP-21469 processor is rated for performance over the temperature range specified in Operating Conditions on Page 16. Table 47 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-to-board measure- ment complies with JESD51-8 ...
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... DDINT DD_DDR2 V R DDEXT V REF DD_THD DD_A S V I/O SIGNALS SS_A Figure 45. ADSP-21469 Ball Configuration - Pin Out Rev. PrB | Page November 2008 Preliminary Technical Data ...
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... Preliminary Technical Data PBGA PINOUT Table 48 lists the pin assignments of the ADSP-21469 SHARC processor. Table 48 PBGA Pin Assignment (Alphabetically by Signal) Signal Ball Signal AMI_ACK R10 BR3 AMI_ADDR0 V16 BR4 AMI_ADDR1 U16 BR5 AMI_ADDR2 T16 BR6 AMI_ADDR3 R16 CLK_CFG0 ...
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... ADSP-21469/ADSP-21469W Table 48 PBGA Pin Assignment (Alphabetically by Signal) Signal Ball Signal EXT EXT INT INT RESET INT RPBA INT TCK K15 INT TDI L15 INT ...
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... Preliminary Technical Data OUTLINE DIMENSIONS The ADSP-21469 is available PBGA lead- free package. BALL A1 PAD CORNER 2.40 2.28 2.16 19.20 19.00 SQ 18.80 17.00 17.05 BSC SQ 16.95 SQ 16.85 1.00 BSC TOP VIEW 1.00 REF DETAIL A 0.61 NOM 0.50 NOM 0.40 MIN SEATING PLANE COMPLIANT TO JEDEC STANDARDS MS-034-BAR-2 Figure 46. 324-Ball Plastic Ball Grid Array [PBGA] ...
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... ADSP-21469/ADSP-21469W AUTOMOTIVE PRODUCTS The ADSP-21469 is available for automotive applications with controlled manufacturing. Note that this special model may have specifica- tions that differ from the general release models. The automotive grade product shown in sentative or authorized ADI product distributor for specific product ordering information. Note that all automotive products are RoHS compliant ...