adsp-21478 Analog Devices, Inc., adsp-21478 Datasheet
adsp-21478
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adsp-21478 Summary of contents
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... PCG SPI/B UART REG Tx/Rx A-D 3-0 DAI Routing/Pins DAI Peripherals Figure 1. Functional Block Diagram One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 Fax: 781.326.3113 SHARC Processor ADSP-21478/ADSP-21479 Automotive Ordering Guide on 69. Internal Memory Block 0 Block 1 Block 2 RAM/ROM RAM/ROM RAM B0D B1D B2D ...
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... ADSP-21478/ADSP-21479 TABLE OF CONTENTS Summary ............................................................... 1 Table Of Contents .................................................... 2 Revision History ...................................................... 2 General Description ................................................. 3 Family Core Architecture ........................................ 4 Family Peripheral Architecture ................................ 7 I/O Processor Features ......................................... 11 System Design .................................................... 12 Development Tools ............................................. 13 Additional Information ........................................ 13 Pin Function Descriptions ....................................... 14 Specifications ........................................................ 19 Operating Conditions .......................................... 19 Electrical Characteristics ....................................... 20 Package Information ........................................... 21 ESD Sensitivity ................................................... 21 Maximum Power Dissipation ................................ 21 Absolute Maximum Ratings .................................. 21 Timing Specifications ...
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... SRC Performance Thermal Diode VISA Support Package Speed 1 Available on the 100-lead package only. (at 266 MHz) 2 The 100-lead packages of the ADSP-21478 and 21479 processors do not contain an external port. 1.88 ns The diagram 7 the ADSP-2147x processors. The core clock domain contains the following features. 16.91 ns 30.07 ns • ...
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... ADSP-21478/ADSP-21479 • Digital peripheral interface that includes two timers wire interface, one UART, two serial peripheral interfaces (SPI), 2 precision clock generators (PCG), three pulse width modulation (PWM) units, and a flexible signal rout- ing unit (DPI SRU). As shown in the block diagram ...
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... Source modules need to be built using the VISA option, in order to allow code generation tools to create these more efficient opcodes. On-Chip Memory The ADSP-21478 processor contains 3 Mbits of internal RAM (Table internal RAM ferent combinations of code and data storage. Each memory block supports single-cycle, independent accesses by the core processor and I/O processor ...
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... Using the DM bus and PM buses, with one bus dedicated to a memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. Table 3. Internal Memory Space (ADSP-21478) Extended Precision Normal or Long Word (64 Bits) Instruction Word (48 Bits) ...
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... IEEE 1394 standard. Only legitimate entertainment content delivered to a source device via another approved copy protection system (such as the DVD content ADSP-21478/ADSP-21479 1 Normal Word (32 Bits) Block 0 ROM (Reserved) 0x0008 0000–0x0008 FFFF Reserved 0x0009 0000– ...
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... ADSP-21478/ADSP-21479 supports 14M words of external memory in bank 0 and 16M words of external memory in bank 1, bank 2, and bank 3. • An SDRAM controller that supports a glueless interface with any of the standard SDRAMs. The SDC supports 62M words of external memory in bank 0, and 64M words of external memory in bank 1, bank 2, and bank 3. ...
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... PWM patterns that produce lower har- monic distortion in three-phase PWM inverters. PWM signals can be mapped to the external port address lines or to the DPI pins. ADSP-21478/ADSP-21479 Digital Applications Interface (DAI) The digital applications interface (DAI) provides the ability to connect various peripherals to any of the DAI pins (DAI_P20– ...
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... ADSP-21478/ADSP-21479 channels (using two stereo devices) per serial port, with a 2 maximum channels. The serial ports permit lit- tle-endian or big-endian transmission formats and word lengths selectable from 3 bits to 32 bits. For the left-justified and I modes, data-word lengths are selectable between 8 bits and 32 bits. Serial ports offer selectable synchronization and transmit modes as well as optional μ ...
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... The SR_SDI input can from any of SPORT0–7 serial data outputs, any of the DAI pins (1–8), and one dedicated pin (SR_SDI). ADSP-21478/ADSP-21479 Note that the SR_SCLK, SR_LAT, and SR_SDI inputs must come from same source except in the case of where SR_SCLK comes from PCGA/B or SR_SCLK and SR_LAT come from PCGA/B ...
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... ADSP-21478/ADSP-21479 FFT Accelerator FFT accelerator implements radix-2 complex/real input, com- plex output FFT with no core intervention. FIR Accelerator The FIR (finite impulse response) accelerator consists of a 1024 word coefficient memory, a 1024 word deep delay line for the data, and four MAC units. A controller manages the accelerator. ...
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... This data sheet provides a general overview of the ADSP-2147x architecture and functionality. For detailed information on the ADSP-2147x family core architecture and instruction set, refer to the SHARC Processor Programming Reference. Rev. PrB | Page March 2010 ADSP-21478/ADSP-21479 ® evaluation plat- ® development and debugging environment ...
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... ADSP-21478/ADSP-21479 PIN FUNCTION DESCRIPTIONS Table 9. Pin Descriptions Name Type ADDR I/O/T (ipu) 23–0 DATA I/O/T (ipu) 15–0 AMI_ACK I (ipu) MS O/T (ipu) 0–1 AMI_RD O/T (ipu) AMI_WR O/T (ipu) FLAG0/IRQ0 I/O (ipu) FLAG1/IRQ1 I/O (ipu) FLAG2/IRQ2/MS2 I/O (ipu) FLAG3/TMREXP/MS3 I/O (ipu) The following symbols appear in the Type column of O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. ...
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... Thermal Diode Anode. When not used, this pin can be left floating. Thermal Diode Cathode. When not used, this pin can be left floating. Table asynchronous input output synchronous, A/D = active drive, Rev. PrB | Page March 2010 ADSP-21478/ADSP-21479 61. Table 2 on Page 3 and Table 53 on Page ...
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... ADSP-21478/ADSP-21479 Table 9. Pin Descriptions (Continued) Name Type 1 MLBCLK I 3 MLBDAT I/O pin mode pin mode. 3 MLBSIG I/O pin mode pin mode 3 MLBDO O/T 3 MLBSO O/T SR_SCLK I (ipu) SR_CLR I (ipu) SR_SDI I (ipu) SR_SDO O (ipu) SR_LAT I (ipu) SR_LDO O/T (ipu) 17–0 RTXI I RTXO O RTCLKOUT ...
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... The BOOT_CFG pins must be valid before RESET (hardware and software) is de- asserted. Note that the BOOT_CFG2 pin is not available on the 100-lead LQFP package. Table asynchronous input output synchronous, A/D = active drive, Rev. PrB | Page March 2010 ADSP-21478/ADSP-21479 Table 2 on Page 3 and Table 53 on Page 64. ...
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... ADSP-21478/ADSP-21479 Table 10. Pin List, Power and Ground Name Type INT EXT RTC 1 GND THD 1 The exposed pad is required to be electrically and thermally connected to GND. Implement this by soldering the exposed pad to a GND PCB land that is the same size as the exposed pad ...
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... EXT 4 Applies to input and bidirectional pins: ADDR23–0, DATA15–0, FLAG3–0, DAI_Px, DPI_Px, BOOT_CFGx, CLK_CFGx, RUNRSTIN, RESET, TCK, TMS, TDI, TRST. 5 Applies to input pin CLKIN. 6 Applies to automotive models only. See Automotive Products on Page 69 ADSP-21478/ADSP-21479 100 MHz Min Max TBD TBD 3.13 3.47 3 ...
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... ADSP-21478/ADSP-21479 ELECTRICAL CHARACTERISTICS 1 Parameter Description 2 V High Level Output Voltage Low Level Output Voltage High Level Input Current Low Level Input Current Low Level Input Current ILPU Pull- Three-State Leakage OZH Current 6 I Three-State Leakage ...
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... Voltage Controlled Oscillator In application designs, the PLL multiplier value should be may cause perma- selected in such a way that the VCO frequency never exceeds f VCO Rev. PrB | Page March 2010 ADSP-21478/ADSP-21479 Rating ) –0 +1.32V _ DD INT ) –0 +1.15V ...
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... ADSP-21478/ADSP-21479 • The product of CLKIN and PLLM must never exceed 1 (max) in Table 15 if the input divider is not enabled VCO (INDIV = 0). • The product of CLKIN and PLLM must never exceed f (max) in Table 15 if the input divider is enabled (INDIV = 1). The VCO frequency is calculated as follows × ...
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... IVDDEVDD t CLKVDD t CLKRST t PLLRST Figure 6. Power-Up Sequencing Rev. PrB | Page March 2010 ADSP-21478/ADSP-21479 sharing these signals on the board must determine if there are any issues that need to be addressed based on this behavior INT , a leakage current of the order of three EXT rail has powered up ...
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... ADSP-21478/ADSP-21479 Clock Input Table 15. Clock Input Parameter Timing Requirements t CLKIN Period CK t CLKIN Width Low CKL t CLKIN Width High CKH t CLKIN Rise/Fall (0 2.0 V) CKRF 3 t CCLK Period CCLK 4 f VCO Frequency VCO CLKIN Jitter Tolerance CKJ 1 Applies only for CLKCFG1– and default values for PLL control bits in PMCTL. ...
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... The following timing specification applies to RESET- OUT/RUNRSTIN pin when it is configured as RUNRSTIN. Table 17. Running Reset Parameter Timing Requirements t Running RESET Pulse Width Low WRUNRST t Running RESET Setup Before CLKIN High SRUNRST CLKIN RUNRSTIN ADSP-21478/ADSP-21479 Min 4 × WRST Figure 9. Reset Min 4 × ...
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... ADSP-21478/ADSP-21479 Interrupts The following timing specification applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0, IRQ1, and IRQ2 interrupts as well as the DAI_P20-1 and DPI_P14-1 pins when they are configured as interrupts. Table 18. Interrupts Parameter Timing Requirement t IRQx Pulse Width IPW DAI_P20– ...
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... SRU. Therefore, the timing specification provided below is valid at the DPI_P14–1 pins. Table 21. Timer Width Capture Timing Parameter Timing Requirement t Timer Pulse Width PWI DPI_P14–1 (TIMER1–0) ADSP-21478/ADSP-21479 Min 2 × t – 1.2 PCLK t PWMO Figure 13. Timer PWM_OUT Timing Min 2 × t PCLK ...
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... ADSP-21478/ADSP-21479 Watch Dog Timer Timing Table 22. Watch Dog Timer Timing Parameter Switching Characteristics t WDT Clock Rising Edge To Watch Dog Timer RESET RST Falling Edge t Reset Pulse Width RSTPW WDT_CLKO Pin to Pin Direct Routing (DAI and DPI) For direct pin connections only (for example DAI_PB01_I to DAI_PB02_O) ...
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... D – PH) × × t – 1 PCGIP t t STRIG HTRIG t PCGIW t DPCGIO t t DTRIGCLK DPCGIO t DTRIGFS Figure 17. Precision Clock Generator (Direct Pin Routing) Rev. PrB | Page March 2010 ADSP-21478/ADSP-21479 Max (2.5 × PCGIP ) 10 + ((2 – PH) × t PCGIP PCGIP t PCGOW Unit ...
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... ADSP-21478/ADSP-21479 Flags The timing specifications provided below apply to ADDR23–0 and DATA7–0 when configured as FLAGS. See Page 14 for more information on flag use. Table 25. Flags Parameter Timing Requirement t FLAGs IN Pulse Width FIPW Switching Characteristic t FLAGs OUT Pulse Width FOPW 1 This is applicable when the Flags are connected to DPI_P14–1, ADDR23–0, DATA7–0 and FLAG3–0 pins. ...
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... Data Enable After SDCLK ENSDAT 1 For f = 266 MHz (core clock to SDCLK ratio = 1:2). CCLK 2 Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDCKE, and DQM. SDCLK DATA (IN) DATA (OUT) CMND ADDR (OUT) ADSP-21478/ADSP-21479 mode when CCLK SDCLK t SSDAT t HSDAT t DCAD t ENSDAT ...
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... ADSP-21478/ADSP-21479 SDRAM Interface Enable/Disable Timing (133 MHz SDCLK) Table 27. SDRAM Interface Enable/Disable Timing Parameter Switching Characteristics t Command Disable After CLKIN Rise DSDC t Command Enable After CLKIN Rise ENSDC t SDCLK Disable After CLKIN Rise DSDCC t SDCLK Enable After CLKIN Rise ENSDCC t Address Disable After CLKIN Rise ...
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... SDS. Test Conditions on Page 61 for the calculation of hold times given capacitive and dc loads. , for deassertion of AMI_ACK (low). For asynchronous assertion of AMI_ACK (high) user must meet t DSAK Rev. PrB | Page March 2010 ADSP-21478/ADSP-21479 Max – 5.12 SDCLK W – – 10 SCDCLK W – ...
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... ADSP-21478/ADSP-21479 ADDR t DARL DATA t AMI_ACK DRLD t DAD t DSAK DAAK Figure 21. Memory Read—Bus Master Rev. PrB | Page March 2010 Preliminary Technical Data t DRHA t SDS t HDRH t RWR ...
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... H SDCLK 2 × t – 5.1 SDCLK t – 4.1 SDCLK SDCLK SDCLK , for deassertion of AMI_ACK (low). For asynchronous assertion of AMI_ACK (high) user must meet t DSAK Rev. PrB | Page March 2010 ADSP-21478/ADSP-21479 Max t – 10 SDCLK W – 7 4.9+ H SDCLK Unit ...
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... ADSP-21478/ADSP-21479 ADDR t DAWL t WDE DATA t DAAK AMI_ACK Preliminary Technical Data t DAWH DDWH t DSAK Figure 22. Memory Write—Bus Master Rev. PrB | Page March 2010 t DWHA t WWR t DATRWH t DDWR t DWHD ...
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... SCKLIW 1 Referenced to the sample edge. 2 Referenced to drive edge. ADSP-21478/ADSP-21479 Serial port signals (SCLK, FS, Data Channel A, Data Channel B) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Rev. PrB | Page March 2010 ...
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... ADSP-21478/ADSP-21479 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE t SCLKIW DAI_P20–1 (SCLK) t DFSIR t t HOFSIR SFSI DAI_P20–1 (FRAME SYNC) t SDRI DAI_P20–1 (DATA CHANNEL A/B) NOTES 1. EITHER THE RISING EDGE OR THE FALLING EDGE OF SCLK (EXTERNAL OR INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. ...
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... DDTENFS t HDTE/I 1ST BIT t DDTLFSE LATE EXTERNAL TRANSMIT FS DRIVE SAMPLE DRIVE t HFSE/I t SFSE/I t DDTENFS t HDTE/I 1ST BIT t DDTLFSE Figure 24. External Late Frame Sync Rev. PrB | Page March 2010 ADSP-21478/ADSP-21479 Min Max 10 0.5 t DDTE/I 2ND BIT t DDTE/I 2ND BIT 1 Unit ns ns ...
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... ADSP-21478/ADSP-21479 Table 33. Serial Ports—Enable and Three-State Parameter Switching Characteristics 1 t Data Enable from External Transmit SCLK DDTEN 1 t Data Disable from External Transmit SCLK DDTTE 1 t Data Enable from Internal Transmit SCLK DDTIN 1 Referenced to drive edge. DRIVE EDGE DAI_P20–1 (SCLK, EXT) DAI_P20– ...
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... The serial clock, data and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins. DAI_P20–1 (SERIAL CLOCK) DAI_P20–1 (FRAME SYNC) DAI_P20–1 (DATA) ADSP-21478/ADSP-21479 Table 34. IDP Min 3.8 2.5 2.5 2.5 (t × ...
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... ADSP-21478/ADSP-21479 Parallel Data Acquisition Port (PDAP) The timing requirements for the PDAP are provided in Table 35. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the PDAP, see the Table 35. Parallel Data Acquisition Port (PDAP) Parameter Timing Requirements ...
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... The serial clock, data and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. DAI_P20–1 (SERIAL CLOCK) DAI_P20–1 (FRAME SYNC) DAI_P20–1 (DATA) ADSP-21478/ADSP-21479 Min TBD TBD TBD TBD (t PCLK ...
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... ADSP-21478/ADSP-21479 Sample Rate Converter—Serial Output Port For the serial output port, the frame-sync is an input and it should meet setup and hold times with regard to the serial clock on the output port. The serial data output has a hold time and Table 37. ASRC, Serial Output Port ...
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... The following timing specifications apply when the ADDR23–8/DPI_14–1 pins are configured as PWM. Table 38. Pulse-Width Modulation (PWM) Timing Parameter Switching Characteristics t PWM Output Pulse Width PWMW t PWM Output Period PWMP PWM OUTPUTS ADSP-21478/ADSP-21479 Min t – 2 PCLK 2 × t – 1.5 PCLK t PWMW t PWMP Figure 30. PWM Timing Rev ...
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... ADSP-21478/ADSP-21479 S/PDIF Transmitter Serial data input to the S/PDIF transmitter can be formatted as 2 left justified right justified with word widths of 16-, 18-, 20-, or 24-bits. The following sections provide timing for the transmitter. S/PDIF Transmitter-Serial Input Waveforms Figure 31 shows the right-justified mode. LRCLK is high for the left channel and low for the right channel ...
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... Frame Rate (FS) SAMPLE EDGE t t SITXCLKW SITXCLK t SISCLKW t SISCLK t SISFS t SISD Figure 34. S/PDIF Transmitter Input Timing Max Oversampling Ratio × Frame Sync <= 1/t 49.2 192.0 Rev. PrB | Page March 2010 ADSP-21478/ADSP-21479 Min Max SIHFS t SIHD SIHFCLK Unit ...
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... ADSP-21478/ADSP-21479 S/PDIF Receiver The following section describes timing as it relates to the S/PDIF receiver. Internal Digital PLL Mode In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the TBD × FS clock. Table 41. S/PDIF Receiver Internal Digital PLL Mode Timing ...
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... SPICLM t SPICHM t HDSPIDM t DDSPIDM MSB t SSPIDM t HSPIDM MSB VALID t DDSPIDM LSB VALID Figure 36. SPI Master Timing Rev. PrB | Page March 2010 ADSP-21478/ADSP-21479 Min Max 8 × t – 2 PCLK 4 × t – 2 PCLK 4 × t – 2 PCLK 2.5 4 × t – 2 PCLK 4 × t – 2 PCLK 4 × ...
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... ADSP-21478/ADSP-21479 SPI Interface—Slave Table 43. SPI Interface Protocol—Slave Switching and Timing Specifications Parameter Timing Requirements t Serial Clock Cycle SPICLKS t Serial Clock High Period SPICHS t Serial Clock Low Period SPICLS t SPIDS Assertion to First SPICLK Edge, CPHASE = 0 or CPHASE = 1 SDSCO t Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 ...
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... DDSPIDS t DSOE MISO (OUTPUT) t CPHASE = 1 SSPIDS MOSI (INPUT) MISO MSB (OUTPUT) t DSOV CPHASE = 0 MOSI MSB VALID (INPUT) ADSP-21478/ADSP-21479 t t SPICLS SPICLKS t SPICHS t DDSPIDS MSB MSB VALID t DDSPIDS LSB t SSPIDS LSB VALID Figure 37. SPI Slave Timing Rev. PrB | Page March 2010 ...
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... ADSP-21478/ADSP-21479 Media Local Bus All the numbers given are applicable for all speed modes (1024Fs, 512Fs and 256Fs for 3-pin; 512Fs and 256Fs for 5-pin) unless otherwise specified. Please refer to MediaLB specification document rev 3.0 for more details. Table 44. MLB Interface, 3-pin Specifications ...
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... MCKH t MCKL t MCKR t MCKF t MLBCLK t MCFDZ t MCDRV t MDZH VALID Figure 38. MLB Timing (3-Pin Interface) Min Rev. PrB | Page March 2010 ADSP-21478/ADSP-21479 Typ Max Unit nspp ...
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... ADSP-21478/ADSP-21479 MLBSIG/ MLBDAT (Rx, Input) MLBCLK MLBSO/ MLBDO (Tx, Output) VALID t DHMCF t DSMCF t t MCKH MCKL t MCKR t MCKF t MLBCLK t MCDRV VALID Figure 39. MLB Timing (5-Pin Interface) MLBCLK t t MPWV MPWV Figure 40. MLB 3-Pin and 5-Pin MLBCLK Pulse Width Variation Timing Rev. PrB | Page March 2010 ...
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... INTERNAL UART RECEIVE INTERRUPT DPI_P14–1 [TxD] TRANSMIT INTERNAL UART TRANSMIT INTERRUPT ADSP-21478/ADSP-21479 ation of internal UART interrupts and the external data operations. These latencies are negligible at the data transmis- sion rates for the UART. DATA (5–8) STOP t RXD START DATA (5–8) STOP (1– ...
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... ADSP-21478/ADSP-21479 Shift Register Table 47. Shift Register Parameter Timing Requirements t SR_SDI Setup Before SR_SCLK Rising Edge SSDI t SR_SDI Hold After SR_SCLK Rising Edge HSDI 1 t DAI_P08–01 (SR_SDI) Setup Before DAI_P08–01 (SR_SCLK) Rising Edge SSDIDAI 1 t DAI_P08–01 (SR_SDI) Hold After DAI_P08–01 (SR_SCLK) Rising Edge ...
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... DSDOPCG1 Figure 43. SR_ SDO Delay t DLDO1 t t AND ARE ALSO VALID FOR DLDO1 DLDO2 AND . DLDOSP1 DLDOSP2 DLDOPCG1 DLDOPCG2 Figure 44. SR_LDO Delay Rev. PrB | Page March 2010 ADSP-21478/ADSP-21479 t HSDI ARE ALSO t DSDO2 ARE ALSO t AND . DSDOPCG2 t DLDO2 t , DLDODAI1 ...
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... ADSP-21478/ADSP-21479 SR_SDCLK OR DAI_P08-01 SR_LAT OR DAI_P08-01 SR_SDI OR DAI_P08-01 SR_LDO THE TIMING PARAMETER SHOWN FOR Figure 45. SR_SDCLK to SR_LAT Setup, Clocks Pulse Width and Maximum Frequency SR_SDCLK OR DAI_P08-01 SR_LAT OR DAI_P08-01 SR_SDO SR_LDO Preliminary Technical Data 1/f t SSCK2LCK 1/f MAX t IS ALSO VALID FOR SSCK2LCK t CLRW t t DSDOCLR2 ...
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... Min 0 4.0 4.7 4.0 4.7 0 250 4.0 4 SUDAT LOW SUSTA HDSTA HIGH Sr t HDDAT Figure 47. Fast and Standard Mode Timing on the TWI Bus Rev. PrB | Page March 2010 ADSP-21478/ADSP-21479 1 Fast Mode Max Min 100 0 0.6 1.3 0.6 0.6 0 100 0.6 1.3 n BUF HDSTA SP t SUSTO P S Max ...
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... ADSP-21478/ADSP-21479 JTAG Test Access Port and Emulation Table 49. JTAG Test Access Port and Emulation Parameter Timing Requirements t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP 1 t System Inputs Setup Before TCK High ...
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... These include DUT OUTPUT Rev. PrB | Page March 2010 ADSP-21478/ADSP-21479 INPUT 1.5V OR OUTPUT Figure 51. Voltage Reference Levels for AC Measurements Figure 50). Figure 54 shows graphically Figure 52, Figure 53, and Figure 54 TBD 0 50 100 150 200 Figure 52 ...
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... ADSP-21478/ADSP-21479 TBD 100 150 Figure 54. Typical Output Delay or Hold vs. Load Capacitance (at Ambient Temperature) THERMAL CHARACTERISTICS The ADSP-2147x processor is rated for performance over the temperature range specified in Operating Conditions on Page 19. Table 50 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-to-board measure- ment complies with JESD51-8 ...
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... Table 52. Thermal Diode Parameters – Transistor Model Symbol Parameter I Forward Bias Current FW I Emitter Current E n Transistor Ideality Q Beta R Series Resistance T ADSP-21478/ADSP-21479 Min Typ TBD TBD TBD TBD TBD TBD TBD Rev. PrB | Page March 2010 Max Unit μA TBD TBD ...
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... ADSP-21478/ADSP-21479 100-LQFP_EP LEAD ASSIGNMENT Table 53 lists the lead names and their default function after reset (in parentheses). Table 53. 100-Lead LQFP_EP Lead Assignments (Numerically by Lead Number) Pin Name Pin No. Pin Name INT CLK_CFG1 2 DPI_P08 BOOT_CFG0 3 DPI_P07 EXT V 5 DPI_P09 ...
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... PIN 25 PIN 26 PIN 50 Figure 55. 100-Lead LQFP_EP Lead Configuration (Top View) PIN 76 PIN 100 PIN 75 GND PAD (PIN 101) PIN 51 PIN 50 PIN 26 Figure 56. 100-Lead LQFP_EP Lead Configuration (Bottom View) Rev. PrB | Page March 2010 ADSP-21478/ADSP-21479 PIN 75 PIN 51 PIN 1 PIN 1 INDICATOR PIN 25 ...
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... ADSP-21478/ADSP-21479 196-BALL BGA BALL ASSIGNMENT Table 54. 196-Ball CSP_BGA Ball Assignment (Numerically by Ball No.) Ball No. Signal Ball No. Signal A1 GND D1 ADDR6 A2 SDCKE D2 ADDR4 A3 SDDQM D3 ADDR1 A4 SDRAS D4 CLK_CFG0 A5 SDWE DATA12 DATA13 DATA10 DATA9 D9 V A10 DATA7 D10 V A11 DATA3 D11 V A12 ...
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... VIEW A 0.22 0.50 0.17 BSC LEAD PITCH COMPLIANT TO JEDEC STANDARDS MS-026-BED-HD (SW-100-2) Dimensions shown in millimeters Rev. PrB | Page March 2010 ADSP-21478/ADSP-21479 76 100 1 EXPOSED PAD 6.00 REF BOTTOM VIEW (PINS UP FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET ...
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... ADSP-21478/ADSP-21479 A1 BALL CORNER 1.50 1.41 1.32 SURFACE-MOUNT DESIGN For industry standard design recommendations, refer to IPC-7351, Generic Requirements for Surface-Mount Design and Land Pattern Standard. Preliminary Technical Data 12.10 12.00 SQ 11. 10.40 BSC SQ 0.80 BSC 0.80 TOP VIEW REF DETAIL A DETAIL A SEATING PLANE BALL DIAMETER * COMPLIANT TO JEDEC STANDARDS MO-205-AE WITH EXCEPTION TO BALL DIAMETER. ...
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... Preliminary Technical Data AUTOMOTIVE PRODUCTS The ADSP-21478 and ADSP-21479 models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these Auto- motive models may have specifications that differ from the commercial models and designers should review the product Specifications section of this datasheet carefully ...
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... ADSP-21478/ADSP-21479 ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR09017-0-3/10 (PrB) Preliminary Technical Data Rev. PrB | Page March 2010 ...