adsp-21267skstz Analog Devices, Inc., adsp-21267skstz Datasheet

adsp-21267skstz

Manufacturer Part Number

adsp-21267skstz

Description

Sharc Processor

Manufacturer

Analog Devices, Inc.

Datasheet

1.ADSP-21267SKSTZ.pdf (44 pages)

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SUMMARY

High performance 32-bit/40-bit floating point processor

Code compatible with all other SHARC DSPs

The ADSP-21267 processes high performance audio while

Audio decoders and post processor-algorithms support.

Single-Instruction Multiple-Data (SIMD) computational archi-

High bandwidth I/O —a parallel port, an SPI port, four serial

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. PrA

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

optimized for high performance audio processing

enabling low system costs

Non-volatile memory can be configured to contain a com-

bination of PCM 96 kHz, Dolby Digital, Dolby Digital EX2,

Dolby Pro Logic IIx, DTS 5.1, DTS ES Discrete 6.1, DTS-ES

Matrix 6.1, DTS Neo:6, MPEG2x BC (2 channel) and others.

See www.analog.com/SHARC for a complete list

tecture—two 32-bit IEEE floating-point/32-bit fixed-point/

40-bit extended precision floating point computational

units, each with a multiplier, ALU, shifter, and register file

ports, a digital audio interface (DAI) and JTAG test port

Preliminary Technical Data

P ROCE SSI NG

ELEME NT

(PE X)

8X4X32

DAG1

JTAG TES T & EMULATIO N

PRO CE SSI NG

ELEMENT

8X 4X32

DAG 2

CORE P ROCE SSO R

(PEY )

PM ADDRE SS BUS

DM ADDRESS BUS

PX REGIS TER

TIMER

SEQ UE NCE R

PROG RAM

INSTRUCTION

32 X 48-BIT

CACHE

Figure 1. FUNCTIONAL BLOCK DIAGRAM

ROUTING

SIG NAL

UNIT

DIGITAL AUDIO INTERFACE

ACQUIS ITION PO RT

ADDR

S PI PORT (1)

P ARALLEL DATA

PRE CI SION CLOCK

SERIAL P ORTS (6)

DATA P ORTS (8)

G ENERATO RS (2)

P M DATA BUS

DM DATA BUS

DMA CONTROLLER

I/O PROCESSOR

TI ME RS (3)

2 2 C HA N N ELS

INPUT

DUAL PORTED MEMORY

S RAM

0.5 MBI T

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel:781/329-4700

DATA

DAI incorporates two precision clock generators (PCG), and

On-chip memory—1M Bit of on-chip SRAM and a dedicated

The ADSP-21267 is available with a 150 MHz core instruction

an input data port (IDP) that includes a parallel data acqui-

sition port (PDAP), and three programmable timers, all

under software control by the signal routing unit (SRU)

3M Bits of on-chip mask-programmable ROM

rate. For complete ordering information, see

Guide on page 43

BLOCK 0

ROM

1.5 MBIT

(MEMO RY MAP PED)

IO D

(32)

DAT A BUFFERS

REGIS TERS

CONTROL,

STATUS, &

I OP

IOA

(18)

DUAL P ORT ED ME MORY

S RAM

0.5 MBIT

SHARC

BLOCK 1

GPIO FLAG S/

IRQ /TIMEXP

D A TA B U S/ GP IO

ADDR

CON TR OL/G PIO

PARALLEL

A D D RE SS/

PORT

RO M

1.5 MBI T

ADSP-21267

DATA

Processor

www.analog.com

Ordering

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