adsp-21266skstz-2b Analog Devices, Inc., adsp-21266skstz-2b Datasheet - Page 6

• Manufacturer Part Number: adsp-21266skstz-2b
• Description: Sharc Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21261/ADSP-21262/ADSP-21266
Instruction Cache
The ADSP-2126x includes an on-chip instruction cache that
enables three-bus operation to fetch an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full-speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.
Data Address Generators with Zero-Overhead Hardware
Circular Buffer Support
The ADSP-2126x’s two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffers in hardware. Circular buffers allow efficient program­
ming of delay lines and other data structures required in digital
signal processing, and are commonly used in digital filters and
Fourier transforms. The two DAGs of the ADSP-2126x contain
sufficient registers to allow the creation of up to 32 circular buff­
ers (16 primary register sets, 16 secondary). The DAGs
automatically handle address pointer wraparound, reduce over­
head, increase performance, and simplify implementation.
Circular buffers can start and end at any memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations for concise programming. For example, the
ADSP-2126x can conditionally execute a multiply, an add, and a
subtract in both processing elements while branching and fetch­
ing up to four 32-bit values from memory—all in a single
instruction.
Rev. E | Page 6 of 48 | July 2008
MEMORY AND I/O INTERFACE FEATURES
The ADSP-2126x adds the following architectural features to
the SIMD SHARC family core:
Dual-Ported On-Chip Memory
The ADSP-21262 and ADSP-21266 contain two megabits of
internal SRAM and four megabits of internal mask-program­
mable ROM. The ADSP-21261 contain one megabit of internal
SRAM and three megabits of internal mask-programmable
ROM. Each block can be configured for different combinations
of code and data storage (see memory maps,
Table
independent accesses by the core processor and I/O processor.
The dual-ported memory, in combination with three separate
on-chip buses, allows two data transfers from the core and one
from the I/O processor, in a single cycle.
The ADSP-2126x is available with a variety of multichannel
surround sound decoders, preprogrammed in ROM memory.
Table 3
Table 3. Multichannel Surround Sound Decoder Algorithms
in On-Chip ROM
The ADSP-2126x’s SRAM can be configured as a maximum of
64K words of 32-bit data, 128K words of 16-bit data, 42K words
of 48-bit instructions (or 40-bit data), or combinations of differ­
ent word sizes up to two megabits. All of the memory can be
accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float­
ing-point storage format is supported that effectively doubles
the amount of data that can be stored on-chip. Conversion
between the 32-bit floating-point and 16-bit floating-point for­
mats is performed in a single instruction. While each memory
block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.
Using the DM bus and PM buses, with one dedicated to each
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache.
Algorithms
PCM
AC-3
DTS 96/24
AAC (LC)
WMAPRO 7.1 96 KHz
MPEG2 BC 2ch
Noise
DPL2x/EX
Neo:6/ES (v2.5046)
5). Each memory block is dual-ported for single-cycle,
shows the configuration of decoder algorithms.
B ROM
Yes
Yes
v2.2
Yes
No
Yes
Yes
DPL2
Yes
C ROM
Yes
Yes
v2.3
Yes
No
Yes
Yes
Yes
Yes
Table 4
No
D ROM
Yes
Yes
v2.3
Coefficients only
Yes
Yes
Yes
Yes
and