adsp-21msp58 Analog Devices, Inc., adsp-21msp58 Datasheet

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adsp-21msp58

Manufacturer Part Number
adsp-21msp58
Description
Dsp Microcomputers
Manufacturer
Analog Devices, Inc.
Datasheet
a
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FEATURES
38 ns Instruction Cycle Time (26 MIPS) from 13.00 MHz
ADSP-2100 Family Code and Function Compatible with
2K
2K
4K
8-Bit Parallel Host Interface Port
Analog Interface Provides:
425 mW Typical Power Dissipation @ 5.0 V @ 38 ns
<1 mW Powerdown Mode with 100 Cycle Recovery
Dual Purpose Program Memory for Both Instruction
Independent ALU, Multiplier/Accumulator, and Barrel
Two Independent Data Address Generators
Powerful Program Sequencer Provides:
Two Double-Buffered Serial Ports with Companding
Programmable 16-Bit Interval Timer with Prescaler
Programmable Wait State Generation
Automatic Booting of Internal Program Memory from
Stand-Alone ROM Execution (ADSP-21msp59 Only)
Single-Cycle Instruction Execution
Single-Cycle Context Switch
Multifunction Instructions
Three Edge- or Level-Sensitive External Interrupts
Low Power Dissipation in Standby Mode
100-Lead TQFP
Crystal
New Instruction Set Enhanced for Bit Manipulation
Instructions, Multiplication Instructions, Biased
Rounding, and Global Interrupt Masking
(ADSP-21msp59 Only)
16-Bit Sigma-Delta ADC and DAC
Programmable Gain Stages
On-Chip Anti-Aliasing & Anti-Imaging Filters
8 kHz Sampling Frequency
65 dB ADC, SNR and THD
72 dB DAC, SNR and THD
and Data Storage
Shifter Computational Units
Zero Overhead Looping
Conditional Instruction Execution
Hardware, One Serial Port (SPORT0) has Automatic
Data Buffering
Byte-Wide External Memory, e.g., EPROM, or
Through Host Interface Port
24 Words of On-Chip Program Memory RAM
16 Words of On-Chip Data Memory RAM
24 Words of On-Chip Program Memory ROM
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
GENERAL DESCRIPTION
The ADSP-21msp58 and ADSP-21msp59 Mixed-Signal Pro-
cessors (MSProcessor
DSPs complete with a high performance analog front end. The
ADSP-21msp58/59 Family is optimized for voice band applica-
tions such as Speech Compression, Speech Processing, Speech
Recognition, Text-to Speech, and Speech-to-Text conversion.
The ADSP-21msp58/59 combines the ADSP-2100 base archi-
tecture (three computation units, data address generators, and
program sequencer) with two serial ports, a host interface port,
an analog front end, a programmable timer, extensive interrupt
capability, and on-chip program and data memory.
The ADSP-21msp58 provides 2K words (24-bit) of program
RAM and 2K words (16-bit) of data memory. The ADSP-
21msp59 provides an additional 4K words (24-bit) of program
ROM. The ADSP-21msp58/59 integrates a high performance
analog codec based on a single chip, voice band codec, the
AD28msp02. Powerdown circuitry is also provided to meet the
low power needs of battery operated portable equipment. The
ADSP-21msp58/59 is available in a 100-pin TQFP package
(thin quad flat package).
In addition, the ADSP-21msp58/59 supports new instructions,
which include bit manipulations–bit set, bit clear, bit toggle,
bit test–new ALU constants, new multiplication instruction
(x squared), biased rounding, and global interrupt masking.
MSProcessor is a registered trademark of Analog Devices, Inc.
GENERATORS
DAG 1 DAG 2
ADDRESS
ALU
DATA
ADSP-2100 BASE
ARITHMETIC UNITS
ARCHITECTURE
MAC
FUNCTIONAL BLOCK DIAGRAM
SEQUENCER
SHIFTER
PROGRAM
DATA MEMORY DATA
PROGRAM MEMORY DATA
DATA MEMORY ADDRESS
PROGRAM MEMORY ADDRESS
DSP Microcomputers
®
ADSP-21msp58/59
DSPs) are fully integrated, single-chip
ADSP-21msp59
PROGRAM
MEMORY
4K x 24
(ROM)
SPORT 0
SERIAL PORTS
MEMORY
PROGRAM
MEMORY
2K x 24
SPORT 1
ADSP-21msp58/59
© Analog Devices, Inc., 1995
TIMER
MEMORY
2K x 16
DATA
INTERFACE
Fax: 617/326-8703
HOST
PORT
POWERDOWN
INTERFACE
CONTROL
ANALOG
LOGIC
FLAG
EXTERNAL
EXTERNAL
ADDRESS
DATA
BUS
BUS

Related parts for adsp-21msp58

adsp-21msp58 Summary of contents

Page 1

... AD28msp02. Powerdown circuitry is also provided to meet the low power needs of battery operated portable equipment. The ADSP-21msp58/59 is available in a 100-pin TQFP package (thin quad flat package). In addition, the ADSP-21msp58/59 supports new instructions, which include bit manipulations– ...

Page 2

... Program memory can store both instructions and data, permit- ting the ADSP-21msp58/59 to fetch two operands in a single cycle, one from program memory and one from data memory. The ADSP-21msp58/59 can fetch an operand from on-chip program memory and the next instruction in the same cycle ...

Page 3

... The ADSP-21msp58/59 processors include two synchronous se- rial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Here is a brief list of the capabilities of the ADSP-21msp58/59 SPORTs. Refer to the ADSP-2100 Family User’s Manual for fur- ther details. • SPORTs are bidirectional with a separate, double-buffered transmit and receive section. • ...

Page 4

... Host Interface Port The ADSP-21msp58/59 host interface port (HIP parallel I/O port that allows for an easy connection to a host processor. Through the HIP, the ADSP-21msp58/59 can be used as a memory-mapped peripheral to a host computer. The HIP can be thought area of dual-ported memory, or mailbox reg- isters, that allows communication between the computational core of the ADSP-21msp58/59 and the host computer ...

Page 5

... Clock Signals The ADSP-21msp58/59 CLKIN input may be driven by a crys- tal TTL-compatible external clock signal. The CLKIN input may not be halted, changed in frequency during operation, or operated at any frequency other the one specified ...

Page 6

... Figure 3. ADSP-21msp58/59 Basic System Configuration CLKOUT signal is enabled and disabled by the CLKODIS bit in the SPORT0 Autobuffer Control Register, DM[0x3FF3]. Because the ADSP-21msp58/59 includes an on-chip oscillator circuit, an external crystal may also be used. The crystal should be connected across the CLKIN and XTAL pins, with two ca- pacitors connected as shown in Figure 4 ...

Page 7

... An external program memory access should always be qualified with the PMS signal. The ADSP-21msp58/59 writes data from its 16-bit registers to 24-bit program memory using the PX register to provide the lower eight bits. When the processor reads data (not instruc- tions) from 24-bit program memory to a 16-bit data register, the lower eight bits are placed in the PX register ...

Page 8

... If GoMode is enabled, the ADSP-21msp58/59 will not halt pro- 3C00 gram execution until it encounters an instruction that requires an external memory access. 3FFF If the ADSP-21msp58/59 is performing an external memory ac- cess when the external device asserts the BR signal, then it will ...

Page 9

... Control Register [0x3FF3]) disables the CLKOUT pin during powerdown. Idle When the ADSP-21msp58/ the Idle Mode, the processor waits indefinitely in a low power state until an interrupt occurs. When an unmasked interrupt occurs serviced; execution then continues with the instruction following the IDLE instruction. ...

Page 10

... In both cases, the I/O processing is interrupt driven; two interrupts are dedicated to the analog interface, one for the ADC receive data and one for the DAC transmit data. The ADSP-21msp58/59 must have an input clock frequency of 13 MHz. At this frequency, analog-to-digital and digital-to-ana- INMAX log converted data is transmitted kHz rate with a single 16-bit word transmitted every 125 s ...

Page 11

... However, when using autobuffer transfers, both interrupts should be enabled. ADSP-21msp58/59 REGISTERS Figure 9 summarizes the ADSP-21msp58/59 registers. Some registers store values. For example, AX0 stores an ALU oper- and; I4 stores a DAG2 pointer. Other registers consist of control bits and fields, or status flags. For example ASTAT contains ...

Page 12

... ADSP-21msp58/59 ASTAT SPORT0 Enable 1 = enabled disabled SPORT1 Enable 1 = enabled disabled SPORT1 Configure 1 = serial port 0 = FI, FO, IRQ0, IRQ1, SCLK 15 0 SSTAT (Read -Only ALU Result Zero AN ALU Result Negative AV ALU Overflow ...

Page 13

... SPORT0 Control Register 0x3FF6 Control Registers –13– ADSP-21msp58/ DWAIT0 1 = Channel Enabled 0 = Channel Ignored 0x3FF8 0x3FF7 ...

Page 14

... ADSP-21msp58/59 CLKODIS CLKOUT Disable Control Bit BIASRND MAC Biased Rounding Control Bit TIREG Transmit Autobuffer I Register Flag Out (Read Only) Internal Serial Clock Generation ISCLK Receive Frame Sync Required RFSR Receive Frame Sync Width RFSW Transmit Frame Sync Required TFSR Transmit Frame Sync Width TFSW ...

Page 15

... Interrupt Enables 1 = Enable 0 = Disable Control Registers –15– ADSP-21msp58/ ARBUF ADC Receive Autobuffer Enable ATBUF DAC Transmit Autobuffer Enable ARMREG ...

Page 16

... ADSP-21msp58/ ADC Offset IG0 ADC Input Gain DABY DAC High Pass Filter Bypass 1 = bypass insert ADBY ADC High Pass Filter Bypass 1 = bypass insert APWD Analog Interface Powerdown 0 = powerdown enable (set both bits enable analog interface ...

Page 17

... Control Registers ADSP-21msp58/59 EXTENDED INSTRUCTION SET The ADSP-21msp58/59 has a number of additional instruc- tions beyond the standard ADSP-2100 Family instruction set. These additional instructions and mathematical operations are described below. Slow IDLE Slow IDLE allows slowing the processor’s internal clock by a factor of 16, 32, 64, or 128 during IDLE ...

Page 18

... Extended ALU and Multiplier Operations The following extended computation operations are available only on the ADSP-21msp58/59 processor. The term “base in- struction set” refers to the computations and instructions avail- able on all ADSP-21xx processors. Additional Constants for ALU Operations ...

Page 19

... VIN and VIN NORM 00-0000-7FFF age (nominal of 2 the ADSP-21msp58/59, which lets the 00-0001-7FFF analog section of the processor operate from a single supply. The input signal should be ac-coupled with an external capaci- tor (C2). The value determined by the input resistance of the analog input (VIN sired cutoff frequency ...

Page 20

... STAR GROUND Figure 13. Voltage Reference Filter Capacitor APPLICATION EXAMPLES ) is produced The ADSP-21msp58/59 is ideal for speech processing applica- N tions where high performance for analog and digital circuitry is required, but board space is severely limited. The cellular radio and has a handset is one application. Here the ADSP-21msp58/59 can ...

Page 21

... Although specified for TTL outputs, all ADSP-21msp58/59 outputs are CMOS-compatible and will drive Idle refers to ADSP-21msp58/59 state of operation during IDLE instruction. Deasserted pins are driven to either V IDLE currents. 7 Three-statable pins: A0-A13, D0-D23, PMS, DMS, BMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RSF1, HD0-HD7/HAD0-HAD7. ...

Page 22

... Permanent damage may occur to devices subjected to high energy electrostatic discharges. The ADSP-21msp58/59 features proprietary ESD protection circuitry to dissipate high energy discharges (Human Body Model). Proper ESD precautions are recommended to avoid performance degradation or loss of function- ality ...

Page 23

... DAC SNR + THD 80 PEAK @ 65dB 60 40 20dB 20dBm0 20 0 –20 – –60 –50 3.17 Figure 14. SNR + THD vs –23– ADSP-21msp58/59 DAC Min (dB) N/A N/A –0.185 –0.170 +0.000 –0.200 –0.300 –0.340 –0.370 N/A N/A Test Condition and 984 1047 and 2 ...

Page 24

... ADSP-21msp58/59 ANALOG INTERFACE ELECTRICAL CHARACTERISTICS Symbol Parameter ADC R Input Resistance I VIN Maximum Input Range MAX DAC: R Output Resistance O V Output DC Offset OOFF V Maximum Voltage Output Swing (p-p) Across R O Single-Ended Differential R Load Resistance L Reference Buffer: Voltage Reference (V ) REF 1 Output Impedence 1 Capacitive Load ...

Page 25

... Parameter Clock Signals t is defined as 0.5 t The ADSP-21msp58/59 uses CK CKI. an input clock with a quency equal to half the instruction rate MHz input clock (which is equivalent to 76.92 ns) yields a 38.46 ns processor cycle (equivalent to 26 MHz). t values within the range of 0.5 t period should be CK ...

Page 26

... ADSP-21msp58/59 Parameter Interrupts and Flags Timing Requirement: IRQx or FI Setup before CLKOUT Low t IFS t IRQx or FI Hold after CLKOUT High IFH Switching Characteristics: t Flag Output Hold after CLKOUT Low FOH t Flag Output Delay from CLKOUT Low FOD NOTES 1 If IRQx and FI inputs meet t and t setup/hold requirements, they will be recognized during the current clock cycle ...

Page 27

... Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships. CLKOUT BR CLKOUT PMS, DMS, BMS,RD REV. 0 Min 1 0.25t 1 0.25t 0 0 0.25t SDB Figure 17. Bus Request–Bus Grant –27– ADSP-21msp58/59 Max Unit + 0.25t + – ...

Page 28

... ADSP-21msp58/59 Parameter Memory Read Timing Requirement Low to Data Valid RDD t A0-A13, PMS, DMS, BMS to Data Valid AA Data Hold from RD High t RDH Switching Characteristic Pulse Width RP t CLKOUT High to RD Low CRD t A0-A13, PMS, DMS, BMS Setup before RD Low ASR ...

Page 29

... CK 0.25t – 0.25t – 0.75t – 0.25t – 0.5t – WRA t t ASW CWR t t WDE DW Figure 19. Memory Write –29– ADSP-21msp58/59 Max Unit 0.25t + WWR t DDR ...

Page 30

... ADSP-21msp58/59 Parameter Serial Ports Timing Requirement: t SCLK Period SCK t DR/TFS/RFS Setup before SCLK Low SCS t DR/TFS/RFS Hold after SCLK Low SCH t SCLK Width SCP in Switching Characteristic: t CLKOUT High to SCLK CC t SCLK High to DT Enable SCDE t SCLK High to DT Valid SCDV t TFS/RFS ...

Page 31

... HA2–0 ADDRESS HSEL HRD HACK DATA HD7– HRDD –31– ADSP-21msp58/59 Max Unit ...

Page 32

... ADSP-21msp58/59 Parameter Host Interface Port Separate Data and Address (HMD1 = 0) Read Strobe and Write Strobe (HMD0 = 1) Timing Requirement: t HA2-0, HRW Setup before Start of Write or Read HSU t Data Setup before End of Write HDSU t Data Hold after End of Write HWDH t HA2-0, HRW Hold after End of Write or Read ...

Page 33

... ALE HSEL HRD t HSHK HACK HDE HAD7–0 ADDRESS t HDD –33– ADSP-21msp58/59 Max Unit ...

Page 34

... ADSP-21msp58/59 Parameter Host Interface Port Multiplexed Data and Address (HMD1 = 1) Read Strobe and Write Strobe (HMD0 = 1) Timing Requirement: t ALE Pulse Width HALP t HAD15-0 Address Setup before ALE Low HASU t HAD15-0 Address Hold after ALE Low HAH t Start of Write or Read after ALE Low ...

Page 35

... VALID FOR ALL TEMPERATURE GRADES. 1 POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS IDLE REFERS TO ADSP-21msp58/59 STATE OF OPERATION DURING EXECUTION IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V POWER REFLECTS DEVICE OPERATING WITH CLKOUT DISABLED TYPICAL POWER DISSIPATION AT 5.0V V INSTRUCTION (CLOCK FREQUENCY REDUCTION). POWER REFLECTS DEVICE OPERATING WITH CLKOUT DISABLED ...

Page 36

... ADSP-21msp58/59 CAPACITIVE LOADING Figures 26 and 27 show the capacitive loading characteristics of the ADSP-21msp58/59 4. 100 C – Figure 26. Typical Output Rise Time vs. Load Capacitance, C (at Maximum Ambient Operating Temperature) L +14 +12 + NOMINAL –2 – ...

Page 37

... L REFERENCE SIGNAL (MEASURED) OH OUTPUT V (MEASURED) OL OUTPUT STOPS Figure 31. Output Enable/Disable –37– ADSP-21msp58/ the interval from when a ENA M EASURED t ENA DIS V OH (MEASURED) V (MEASURED) –0.5V 2. (MEASURED) +0.5V 1.0V OL ...

Page 38

... ADSP-21msp58/59 100 1 D15 D16 D17 D18 D19 D20 D21 D22 D23 VDD GND PMS DMS BMS RD WR HD7 HD6 HD5 HD4 HD3 HD2 HD1 HD0 HA2/ALE 25 26 PIN CONFIGURATION 100-Lead Thin Plastic Quad Flatpack (TQFP) TOP VIEW (PINS DOWN) –38– ...

Page 39

... HACK A3 66 HMD1 A4 67 HMD0 IRQ2 RESET A7 70 MMAP A8 71 GNDA A9 72 REF_FILTER A10 73 VINAUX A11 74 DECOUPLE A12 75 VINNORM –39– ADSP-21msp58/59 TQFP Pin Number Name 76 VCC 77 VREF 78 VOUTP 79 VOUTN 80 GND 81 BMODE 82 PWD ...

Page 40

... Ambient Temperate Part Number Range ADSP-21msp58BST-104 – +85 C *Refer to the section titled “Ordering Procedure for ADSP-21msp59 ROM Processors” for information about ordering ROM coded parts. OUTLINE DIMENSIONS Dimensions shown in millimeters and (inches) 16.25 (0.640) SQ 15.75 (0.620) 1.60 (0.063) MAX 14 ...

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