at40kal ATMEL Corporation, at40kal Datasheet

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at40kal

Manufacturer Part Number
at40kal
Description
At40kal Military Reprogrammable Fpgas With Freeram
Manufacturer
ATMEL Corporation
Datasheet
Features
Functionally and Pin Compatible with the Atmel Rad Hard AT40KAL Series
Ultra High Performance
FreeRAM
384 PCI Compliant I/Os
8 Global Clocks
Cache Logic
Package Options
Industry-standard Design Tools
Intellectual Property Cores
Easy Migration to Atmel Gate Arrays for High Volume Production
Supply Voltage 3.3V
Design Tools
QML Q Quality Grade
– System Speeds to 85 MHz
– Array Multipliers > 45 MHz
– 14 ns Flexible SRAM
– Internal Tri-state Capability in Each Cell
– Flexible, Single/Dual Port, Sync/Async 14 ns SRAM
– 18432 Bits of Distributed SRAM Independent of Logic Cells for AT40KAL
– Programmable Output Drive
– Fast, Flexible Array Access Facilitates Pin Locking
– Fast, Low Skew Clock Distribution
– Programmable Rising/Falling Edge Transitions
– Distributed Clock Shutdown Capability for Low Power Management
– Global Reset/Asynchronous Reset Options
– 4 Additional Dedicated PCI Clocks
– Unlimited Reprogrammability via Serial or Parallel Modes
– Enables Adaptive Designs
– Enables Fast Vector Multiplier Updates
– Quick-Change
– MQFPF160
– Seamless Integration (Libraries, Interface, Full Back-annotation) with Exemplar
– Timing Driven Placement & Routing
– Automatic/Interactive Multi-chip Partitioning
– Fast, Efficient Synthesis
– Over 75 Automatic Component Generators Create 1000s
– Fir Filters, UARTs, PCI, FFT and Other System Level Functions
– ATDH40M: Mother Board
– ATDH40D160M: Daughter Board for MQFPF160
– ATDS2100PC: IDS Software Design Kit
– ATDH 2225: AT17 Series Configuration Memory ISP Downloadable
Mentor
of Reusable, Fully Deterministic Logic and RAM Functions
®
, Synplicity
®
Dynamic Full/Partial Reconfigurability In-System
Tools for Fast, Easy Design Changes
®
,
Reprogrammable
FPGAs with
FreeRAM
Military
AT40KAL
Preliminary
Rev. 4263B–AERO–06/03
1

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at40kal Summary of contents

Page 1

... Internal Tri-state Capability in Each Cell ™ • FreeRAM – Flexible, Single/Dual Port, Sync/Async 14 ns SRAM – 18432 Bits of Distributed SRAM Independent of Logic Cells for AT40KAL • 384 PCI Compliant I/Os – Programmable Output Drive – Fast, Flexible Array Access Facilitates Pin Locking • ...

Page 2

... The AT40KAL FPGA offers a patented distributed SRAM capability where the RAM can be used without losing logic resources. Multiple independent, synchronous or asynchronous, dual port or single port RAM functions (FIFO, scratch pad, etc.) can be created using Atmel’ ...

Page 3

... The patented AT40KAL series architecture employs a symmetrical grid of small yet powerful cells connected to a flexible busing network. Independently controlled clocks and resets govern every column of cells. The array is surrounded by programmable I/O. ...

Page 4

... Note: 1. The right-most column can only be used as single-port RAM. Figure 1. Symmetrical Array Surrounded by I/O (AT40K20) = I/O Pad = AT40K Cell Note: AT40KAL has registered I/Os. Group enable every sector for tri-states on obuf’s. (1) , with either synchronous or asynchro- = Repeater Row = FreeRAM = Repeater Column 4263B–AERO–06/03 ...

Page 5

... Repeaters regenerate signals and can connect any bus to any other bus (all path- ways are legal) on the same plane. Each repeater has connections to two adjacent local-bus segments and two express-bus segments. This is done automatically using the integrated development system (IDS) tool. AT40KAL (1) = Vertical Repeater RV ...

Page 6

... Express/Express turns are implemented through separate pass gates distributed throughout the array. Some of the bus resource on the AT40KAL is used as a dual-function resource. Table 2 shows which buses are used in a dual-function mode and which bus plane is used. The AT40KAL software tools are designed to accommodate dual-function buses in an effi- cient manner ...

Page 7

... Figure 3. Busing Plane (One of Five) 4263B–AERO–06/03 = AT40K/40KAL AT40KAL = Local/Local or Express/Express Turn Point = Row Repeater = Column Express Express bus bus Local bus AT40KAL 7 ...

Page 8

... CEL CEL CEL CEL (a) Cell-to-cell Connections AT40KAL 8 Figure 4(a) depicts direct connections between a cell and its eight nearest neighbors. Figure 4(b) shows the connections between a cell and five horizontal local buses (1 per busing plane) and five vertical local buses (1 per busing plane). ...

Page 9

... This allows bus signals to switch planes to achieve greater routability five simultaneous local/local turns are possible. The AT40KAL FPGA core cell is a highly configurable logic block based around two 3- input LUTs ( ROM), which can be combined to produce one 4-input LUT. This means that any core cell can implement two functions of 3 inputs or one function of 4 inputs ...

Page 10

... CARRY AT40KAL 10 Synthesis Mode. This mode is particularly important for the use of VHDL design. VHDL Synthesis tools generally Q (Registered) will produce as their output large amounts of random logic and/or functions. Having a 4-input LUT structure gives efficient Q random logic optimization without the delays associated with larger LUT structures ...

Page 11

... RAM. Each bit in the dual-port RAM is also a transpar- ent latch. The front-end latch and the memory latch together form an edge-triggered flip flop. When a nibble (bit = 7) is (Write) addressed and LOAD is logic 1 and WE is logic 0, AT40KAL CLK CLK ...

Page 12

... Din Clear RAM-Clear Byte Figure 9 on page 13 shows an example of a RAM macro constructed using AT40KAL’s FreeRAM cells. The macro shown is a 128 x 8 dual-ported asynchronous RAM. Note the very small amount of external logic required to complete the address decoding for the macro. Most of the logic cells (core cells) in the sectors occupied by the RAM will be unused: they can be used for other logic in the design ...

Page 13

WE 2-to-4 Decoder Write Address Din(0) Din(1) Din(2) Din(3) Din Dout Ain Aout WEN OEN Din(4) Din(5) Din(6) Din(7) Din Dout Ain Aout WEN OEN Din Dout Din Dout Aout Ain Ain Aout WEN WEN OEN OEN Din Dout Din ...

Page 14

... Clocking Scheme AT40KAL 14 There are eight Global Clock buses (GCK1 - GCK8) on the AT40KAL FPGA. Each of the eight dedicated Global Clock buses is connected to one of the dual-use Global Clock pins. Any clocks used in the design should use global clocks where possible: this can be done by using Assign Pin Locks to lock the clocks to the Global Clock locations. ...

Page 15

... Half length at edge) 4263B–AERO–06/03 “1” Sector Clock Mux Global Clock Line (Buried) “1” Repeater Sector Clock Mux “1” “1” } FCK (2 per Edge Column of the Array)   GCK1 - GCK8  Column Clock Mux AT40KAL 15 ...

Page 16

... Set/Reset Scheme AT40KAL 16 The AT40KAL family reset scheme is essentially the same as the clock scheme except that there is only one Global Reset. A dedicated Global Set/Reset bus can be driven by any User I/O, except those used for clocking (Global Clocks or Fast Clocks). The auto- matic placement tool will choose the reset net with the most connections to use the glo- bal resources ...

Page 17

... Figure 11. Set/Reset (for One Column of Cells) Repeater Express Bus (Plane 5; Half length at edge) 4263B–AERO–06/03 Each Cell has a programmable Set or Reset Sector Set/Reset Mux “1” Global Set/Reset Line (Buried) “1” “1” “1” Any User I/O can drive Global Set/Reset line AT40KAL 17 ...

Page 18

... The Source Selection mux selects the source for the output signal of an I/O. See Figure 12 on page 21. The AT40KAL has three kinds of I/Os: Primary I/O, Secondary I/O and a Corner I/O. Every edge cell except corner cells on the AT40KAL has access to one Primary I/O and two Secondary I/Os. Every logic cell at the edge of the FPGA array has a direct orthogonal connection to and from a Primary I/O cell ...

Page 19

... Logic cells at the corner of the FPGA array have direct-connect access to five separate I/Os: 2 Primary, 2 Secondary and 1 Corner I/O. Corner I/Os are like an extra Secondary I/O at each corner of the array. With the inclusion of Corner I/Os, an AT40KAL FPGA with core cells always has 8n I/Os. As the diagram shows, Corner I/Os can be accessed both from the corner logic cell and the horizontal and vertical busing networks running along the edges of the array ...

Page 20

... Figure 12. South I/O (Mirrored for North I/O) AT40KAL 20 (a) Primary I/O (a) Primary I/O (b) Secondary I/O 4263B–AERO–06/03 ...

Page 21

... Figure 13. West I/O (Mirrored for East I/O) PULL-UP PAD PULL-DOWN 4263B–AERO–06/03 a. Primary I/0 "0" "1" "0" "1" b. Secondary I/O AT40KAL CELL CELL 21 ...

Page 22

... Figure 14. Northwest Corner I/O (Similar NE/SE/SW Corners) VCC DRIVE TRI-ST ATE RST PULL-UP PAD PULL-DOWN AT40KAL 22 PAD VCC GND DRIVE TTL/CMOS TRI-ST ATE SCHMITT DELAY ICLK OCLK RST RST "0" "1" "0" "1" PAD GND TTL/CMOS SCHMITT DELAY ICLK ...

Page 23

... Operating Temperature V Power Supply CC Input Voltage Level (CMOS) AT40KAL Stresses beyond those listed under Absolute Maximum Ratings may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under oper- ating conditions is not implied ...

Page 24

... OZH Leakage Current Low-level Tri-state Output I OZL Leakage Current I Standby Current CC Consumption C Input Capacitance IN Note: 1. Parameter based on characterization and simulation not tested in production. Power-On Power Supply Requirements AT40KAL 24 Conditions CMOS TTL CMOS TTL min ...

Page 25

... PDHL IH DD AT40KAL Units 1.2 ns 1.2 ns 1.2 ns 1.2 ns 0.5 ns 0.5 ns Notes 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load ...

Page 26

... Path (max) pad -> x/y (max) pad -> x/y (max) pad -> x/y (max) pad -> x/y (max) x/y/E/L -> pad (max) x/y/E/L -> pad (max) x/y/E/L -> pad (max) oe -> pad (max) oe -> pad (max) oe -> pad (max) oe -> pad (max) oe -> pad (max) oe -> pad AT40KAL Units 2.7 ns 4.9 ns 8.1 ns 11.3 ns 11.2 ns 8.4 ns 6.9 ns 12.2 ns 1.9 ns 7.8 ns 3.3 ns 6.1 ns 3.3 ns 4263B– ...

Page 27

... IH Path Device pad -> clock AT40KAL pad -> clock AT40KAL clock -> colclk AT40KALAT 40KAL colclk -> secclk AT40KAL colclk -> secclk AT40KAL clock pad -> out AT40KAL clock pad -> out AT40KAL of 1 the pad to the internal AT40KAL of 50 Units Notes 2.5 ns rising edge clock 1 ...

Page 28

... Write/Read t (max) PD Write/Read t (max) PD Read t (max) PD Read t (max) PZX Read t (max) PXZ AT40KAL 28 Path AT40KAL cycle time 14 we 5.5 we 5.5 wr addr setup -> we 5.8 wr addr hold -> we 0.0 din setup -> we 5.0 din hold -> we 0.0 oe hold -> we 0.0 din -> dout 7.0 rd addr -> dout 4.8 oe -> dout 3.3 oe -> dout 3 ...

Page 29

... Dual Port Read RD ADDR OE DATA 4263B–AERO–06/03 t CLKH t t WCS WCH t t ACS ACH OXZ t t DCS DCH t CLKH t t WCH WCS t t ACS ACH DCS DCH OZX AD AT40KAL OZX AD t CYC t CLKL OXZ 29 ...

Page 30

... FreeRAM Synchronous Timing Characteristics Single Port Write/Read CLK WE ADDR OE DATA Dual Port Write with Read CLK WE WR ADDR WR DATA RD ADDR = WR ADDR 1 RD DATA AT40KAL 30 t CLKH t t WCS WCH t t ACS ACH OXZ t t DCS DCH t CLKH t t WCH WCS ...

Page 31

... Dual Port Read RD ADDR OE DATA 4155A–AERO–06/ OZX AD AT40KAL/ OXZ 31 ...

Page 32

... I/O50 I/O51 I/O52 I/O53 I/O54 GND I/O55 I/O56 10 I/O57 I/O58 11 I/O59 12 I/O60 13 VCC GND 14 I/O61 I/O62 I/O63 I/O64 I/O65 AT40KAL/EL MQFPF160 384 I/O MQFPF160 I/O66 GND I/O67 I/O68 VCC I/O69 I/O70 I/O71 I/O72, FCK2 GND I/O73 I/O74 I/O75 I/O76 I/O77 15 I/O78 16 GND ...

Page 33

... I/O109 I/O110 I/O111 I/O112 I/O113 I/O114 I/O115 I/O116 I/O117 I/O118 I/O119 I/O120 I/O121 I/O122 I/O123 I/O124 I/O125 I/O126 I/O127 I/O128 I/O129 I/O130 I/O131 I/O132 AT40KAL/EL 33 MQFPF160 384 I/O GND 43 VCC I/O133 44 I/O134 45 I/O135 46 I/O136 47 I/O137 48 I/O138 GND GND I/O139 I/O140 I/O141 I/O142 ...

Page 34

... I/O249 91 I/O250 I/O251 I/O252 92 VCC 93 GND I/O253 I/O254 94 I/O255 I/O256 95 I/O257 I/O258 GND I/O259 (D2) I/O260 VCC I/O261 I/O262,FCK4 I/O263 AT40KAL/EL 384 I/O MQFPF160 I/O264 GND 110 I/O265 I/O266 I/O267 I/O268 I/O269 96 I/O270 97 GND I/O271 I/O272 98 I/O273 111 99 I/O274 112 100 I/O275 101 ...

Page 35

... I/O306 I/O307 I/O308 I/O309 I/O310 I/O311 I/O312 I/O313 I/O314 I/O315 I/O316 I/O317 I/O318 I/O319 I/O320 I/O321 I/O322 I/O323 I/O324 I/O325 I/O326 I/O327 I/O328 AT40KAL/EL 35 MQFPF160 384 I/O I/O329 I/O330 GND 127 I/O331 I/O332 128 (A3) I/O333 I/O334 I/O335 VCC (A6) GND I/O336 (1) (1) 121 NC ...

Page 36

... Package MQFPF 160 (1) MQFPF 256 (1) MQFPF 352 Note: 1. Contact Atmel for availabilty. Part Number AT40KAL040KW1M-E AT40KAL040KW1M AT40KAL040KW1MMQ AT40KAL 130 193 289 Temperature Range Quality Flow 25°C Engineering Samples -55° to +125°C Standard Mil -55° to +125°C Mil Std 883 Level B 4263B–AERO–06/03 ...

Page 37

... Package Drawing Multilayer Quad Flat Pack (MQFP) 160-pin 4263B–AERO–06/03 AT40KAL 37 ...

Page 38

... FAX (81) 3-3523-7581 Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...

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