ep2sgx30c Altera Corporation, ep2sgx30c Datasheet - Page 287
ep2sgx30c
Manufacturer Part Number
ep2sgx30c
Description
Stratix Ii Gx Device Data Sheet
Manufacturer
Altera Corporation
Datasheet
1.EP2SGX30C.pdf
(314 pages)
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Altera Corporation
October 2007
Notes to
(1)
(2)
(3)
(4)
1.5-V differential
HSTL Class II
3.3-V PCI
3.3-V PCI-X
LVDS
LVPECL
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
3.3-V LVCMOS
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.2-V HSTL
Table 4–97. Maximum Output Clock Toggle Rate Derating Factors (Part 5 of 5)
I/O Standard
For LVDS output on row I/O pins the toggle rate derating factors apply to loads larger than 5 pF. In the derating
calculation, subtract 5 pF from the intended load value in pF for the correct result. For a load less than or equal to
5 pF, refer to
1.2-V HSTL is only supported on column I/O pins on -3 devices.
Differential HSTL and SSTL is only supported on column clock and DQS outputs.
LVPECL is only supported on column clock outputs.
Table
(4)
(2)
(3)
4–97:
Tables 4–91
OCT 50 Ω
OCT 50 Ω
OCT 50 Ω
OCT 50 Ω
OCT 50 Ω
OCT 50 Ω
OCT 25 Ω
OCT 50 Ω
OCT 25 Ω
OCT 50 Ω
Strength
16 mA
18 mA
20 mA
Drive
through
134
134
133
207
151
300
157
121
100
95
95
94
56
61
95
-3
4–95
-
-
Column I/O Pins
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
for output toggle rates.
101
100
101
177
177
152
274
165
316
171
134
101
123
110
-4
-
-
-
101
100
101
177
177
152
274
165
316
171
134
101
123
110
-5
-
-
-
155
133
207
151
300
157
121
100
56
-3
-
-
-
-
-
-
-
-
(1)
Row I/O Pins
Stratix II GX Device Handbook, Volume 1
155
152
274
165
316
171
134
101
123
(1)
-4
-
-
-
-
-
-
-
-
DC and Switching Characteristics
155
152
274
165
316
171
134
101
123
(1)
-5
-
-
-
-
-
-
-
-
101
104
143
143
134
134
147
235
153
263
174
106
96
77
58
59
95
-3
Dedicated Clock
Outputs
101
100
101
177
177
134
134
152
274
165
316
171
134
101
123
110
-4
-
4–117
101
100
101
177
177
134
134
152
274
165
316
171
134
101
123
110
-5
-
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