ep2a40b724i8 Altera Corporation, ep2a40b724i8 Datasheet - Page 25

• Manufacturer Part Number: ep2a40b724i8
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

Altera Corporation
Figure 13. Product-Term Logic in ESB
Note ot
(1)
From
Adjacent
LAB
PLL outputs cannot drive data input ports.
Figure
Local
Interconnect
13:
65
Dedicated Clocks
Global Signals
Macrocells
APEX II macrocells can be configured individually for either sequential or
combinatorial logic operation. The macrocell consists of three functional
blocks: the logic array, the product-term select matrix, and the
programmable register.
Combinatorial logic is implemented in the product terms. The product-
term select matrix allocates these product terms for use as either primary
logic inputs (to the OR and XOR gates) to implement combinatorial
functions, or as parallel expanders to be used to increase the logic
available to another macrocell. One product term can be inverted; the
Quartus II software uses this feature to perform DeMorgan’s inversion for
more efficient implementation of wide OR functions. The Quartus II
Compiler can use a NOT-gate push-back technique to emulate an
asynchronous preset.
4
8
(1)
APEX II Programmable Logic Device Family Data Sheet
Figure 14
9
32
2
2
2
shows the APEX II macrocell.
MegaLAB Interconnect
ENA[1..0]
CLK[1..0]
CLRN[1..0]
Macrocell
Inputs (1 to 16)
16
To Row
and Column
Interconnect
25