ep2a40b724i8 Altera Corporation, ep2a40b724i8 Datasheet - Page 3

• Manufacturer Part Number: ep2a40b724i8
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

Altera Corporation
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Enhanced internal memory structure
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Device configuration
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Flexible clock management circuitry with eight general-purpose PLL
outputs
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Advanced interconnect structure
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Advanced software support
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Programmable output drive for 3.3-V LVTTL at 4 mA, 12 mA,
24 mA, or I/O standard levels
Programmable output slew-rate control reduces switching noise
Hot-socketing operation supported
Pull-up resistor on I/O pins before and during configuration
High-density 4,096-bit ESBs
Dual-Port+ RAM with bidirectional read and write ports
Support for many other memory functions, including CAM,
FIFO, and ROM
ESB packing mode partitions one ESB into two 2,048-bit blocks
Fast byte-wide synchronous configuration minimizes in-circuit
reconfiguration time
Device configuration supports multiple voltages (either 3.3 V
and 2.5 V or 1.8 V)
Four general-purpose PLLs with two outputs per PLL
Built-in low-skew clock tree
Eight global clock signals
ClockLock
ClockBoost
and division (by 1 to 256)
ClockShift
delay shifting with coarse (90°, 180°, or 270°) and fine (0.5 to
1.0 ns) resolution
All-layer copper interconnect for high performance
Four-level hierarchical FastTrack
predictable interconnect delays
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
Interleaved local interconnect allowing one LE to drive 29 other
LEs through the fast local interconnect
Software design support and automatic place-and-route
provided by the Altera
Windows-based PCs, Sun SPARCstations, and HP 9000
Series 700/800 workstations
Altera MegaCore
Program (AMPP
architecture
TM
TM
APEX II Programmable Logic Device Family Data Sheet
TM
feature providing programmable clock phase and
feature reducing clock delay and skew
feature providing clock multiplication (by 1 to 160)
SM
®
) megafunctions optimized for APEX II
functions and Altera Megafunction Partners
®
Quartus
®
TM
interconnect structure for fast,
II development system for
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