ep2a40b724i8 Altera Corporation, ep2a40b724i8 Datasheet - Page 63

• Manufacturer Part Number: ep2a40b724i8
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

Altera Corporation
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
Note to
(1)
SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and examined during
EXTEST
BYPASS
USERCODE
IDCODE
HIGHZ
CLAMP
ICR instructions
SignalTap
instructions
Table 16. APEX II JTAG Instructions
JTAG Instruction
Bus hold and weak pull-up features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
Table
(1)
(1)
(1)
16:
normal device operation, and permits an initial data pattern to be output at the device pins.
Also used by the SignalTap embedded logic analyzer.
Allows the external circuitry and board-level interconnections to be tested by forcing a test
pattern at the output pins and capturing test results at the input pins.
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data
to pass synchronously through selected devices to adjacent devices during normal device
operation.
Selects the 32-bit USERCODE register and places it between the TDI and TDO pins,
allowing the USERCODE to be serially shifted out of TDO.
Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE
to be serially shifted out of TDO.
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data
to pass synchronously through selected devices to adjacent devices during normal device
operation, while tri-stating all of the I/O pins.
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data
to pass synchronously through selected devices to adjacent devices during normal device
operation while holding I/O pins to a state defined by the data in the boundary-scan
register.
Used when configuring an APEX II device via the JTAG port with a MasterBlaster
ByteBlasterMV
embedded processor.
Monitors internal device operation with the SignalTap embedded logic analyzer.
All APEX II devices provide JTAG BST circuitry that complies with the
IEEE Std. 1149.1-1990 specification. JTAG boundary-scan testing can be
performed before or after configuration, but not during configuration.
APEX II devices can also use the JTAG port for configuration with the
Quartus II software or with hardware using either Jam
and Programming Language (STAPL) Files (.jam) or Jam Byte-Code Files
(.jbc). Finally, APEX II devices use the JTAG port to monitor the logic
operation of the device with the SignalTap embedded logic analyzer.
APEX II devices support the JTAG instructions shown in
The APEX II device instruction register length is 10 bits. The APEX II
device USERCODE register length is 32 bits.
boundary-scan register length and device IDCODE information for
APEX II devices.
TM
download cable, or when using a Jam File or Jam Byte-Code File via an
APEX II Programmable Logic Device Family Data Sheet
Description
Tables 17
TM
and
Table
Standard Test
18
show the
16.
TM
or
63