cy8c20436 Cypress Semiconductor Corporation., cy8c20436 Datasheet

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cy8c20436

Manufacturer Part Number
cy8c20436
Description
Capsense Applications Ic Mcu 8k Flash 1k Sram 24qfn
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Features
Cypress Semiconductor Corporation
Document Number: 001-12696 Rev. *E
1.71V to 5.5V Operating Range
Low Power CapSense™ Block
Powerful Harvard Architecture Processor
Flexible On-Chip Memory
Full Speed USB
Precision, Programmable Clocking
Programmable Pin Configurations
Configurable Capacitive Sensing Elements
Supports Combination of CapSense Buttons, Sliders, Touch-
pads, Touch Screens, and Proximity Sensor
M8C Processor Speeds Running to 24 MHz
Low Power at High Speed
Interrupt Controller
Temperature Range: -40°C to +85°C
Three Program/Data Storage Size Options:
• CY8C20x36: 8K Flash / 1K SRAM
• CY8C20x46, CY8C20x96: 16K Flash / 2K SRAM
• CY8C20x66: 32K Flash / 2K SRAM
50,000 Flash Erase/Write Cycles
Partial Flash Updates
Flexible Protection Modes
In-System Serial Programming (ISSP)
Available on CY8C20646, CY8C20666, CY8C20x96 Only
12 Mbps USB 2.0 Compliant
Eight Unidirectional Endpoints
One Bidirectional Control Endpoint
Dedicated 512 Byte Buffer
Internally Regulated at 3.3V
Internal Main Oscillator: 6/12/24 MHz ± 5%
Internal Low Speed Oscillator at 32 kHz for Watchdog and
Sleep Timers
Precision 32 kHz Oscillator for Optional External Crystal
0.25% Accuracy for USB with No External Components
(CY8C20646, CY8C20666, CY8C20x96 only)
Up to 36 GPIO (Depending on Package)
Dual Mode GPIO: All GPIO Support Digital I/O and Analog
Input
25 mA Sink Current on All GPIO
Pull up, High Z, Open Drain Modes on All GPIO
CMOS Drive Mode (5 mA Source Current) on Ports 0 and 1:
• 20 mA (at 3.0V) Total Source Current on Port 0
• 20 mA (at 3.0V) Total Source Current on Port 1
Selectable, Regulated Digital I/O on Port 1
Configurable Input Threshold on Port 1
Hot Swap Capability on all Port 1 GPIO
198 Champion Court
Versatile Analog Mux
Additional System Resources
Complete Development Tools
Package Options
Common Internal Analog Bus
Simultaneous Connection of I/O
High PSRR Comparator
Low Dropout Voltage Regulator for All Analog Resources
I2C Slave:
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• No Clock Stretching Required (under most conditions)
• Implementation During Sleep Modes with Less Than
• Hardware Address Validation
SPI™ Master and Slave: Configurable 46.9 kHz to 12 MHz
Three 16-Bit Timers
Watchdog and Sleep Timers
Internal Voltage Reference
Integrated Supervisory Circuit
8-bit Delta-Sigma Analog-to-Digital Converter
Two General Purpose High Speed, Low Power Analog Com-
parators
Free Development Tool (PSoC Designer™)
Full Featured, In-Circuit Emulator and Programmer
Full Speed Emulation
Complex Breakpoint Structure
128K Trace Memory
CY8C20x36:
• 16-Pin 3 x 3 x 0.6 mm QFN
• 24-Pin 4 x 4 x 0.6 mm QFN
• 32-Pin 5 x 5 x 0.6 mm QFN
• 48-Pin SSOP
• 48-Pin 7 x 7 x 1.0 mm QFN
CY8C20x46:
• 16-Pin 3 x 3 x 0.6 mm QFN
• 24-Pin 4 x 4 x 0.6 mm QFN
• 32-Pin 5 x 5 x 0.6 mm QFN
• 48-Pin SSOP
• 48-Pin 7 x 7 x 1.0 mm QFN (with USB)
CY8C20x96:
• 24-Pin 4 x 4 x 0.6 mm QFN (with USB)
• 32-Pin 5 x 5 x 0.6 mm QFN (with USB)
CY8C20x66:
• 32-Pin 5 x 5 x 0.6 mm QFN
• 48-Pin 7 x 7 x 1.0 mm QFN (with USB)
• 48-Pin SSOP
100 µA
San Jose
CapSense
,
CA 95134-1709
CY8C20X36/46/66/96
®
Applications
Revised April 24, 2009
408-943-2600
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cy8c20436 Summary of contents

Page 1

Features 1.71V to 5.5V Operating Range ■ Low Power CapSense™ Block ■ Configurable Capacitive Sensing Elements ❐ Supports Combination of CapSense Buttons, Sliders, Touch- ❐ pads, Touch Screens, and Proximity Sensor Powerful Harvard Architecture Processor ■ M8C Processor Speeds Running ...

Page 2

Logic Block Diagram PSoC CORE SYSTEM BUS 1K/2K Supervisory ROM (SROM) SRAM Interrupt Controller 6/12/24 MHz Internal Main Oscillator CAPSENSE SYSTEM Two Comparators SYSTEM BUS I2C USB Slave References Document Number: 001-12696 Rev. *E Port 4 Port 3 Port 2 ...

Page 3

PSoC Functional Overview The PSoC family consists of on-chip Controller devices. These devices are designed to replace multiple traditional MCU-based components with one, low cost single-chip programmable component. A PSoC device includes configurable analog and digital blocks, and programmable ...

Page 4

Additional System Resources System Resources, some of which are listed in the previous sections, provide additional capability useful to complete systems. Additional resources include low voltage detection and power on reset. The merits of each system resource are listed here: ...

Page 5

Development Tools ® PSoC Designer is a Microsoft Windows-based, integrated development environment for the Programmable System-on- Chip (PSoC) devices. The PSoC Designer IDE and application runs on Windows XP and Windows Vista. This system provides design database management by project, ...

Page 6

Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification ...

Page 7

Document Conventions Acronyms Used The following table lists the acronyms that are used in this document. Table 1. Acronyms Acronym Description AC alternating current API application programming interface CPU central processing unit DC direct current FSR full scale range GPIO ...

Page 8

Pinouts The CY8C20x36/46/66/96 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of Digital I/O and connection to the common analog bus. ...

Page 9

QFN Table 3. Pin Definitions - CY8C20336, CY8C20346 Type Pin Name No. Digital Analog 1 I/O I P2[5] Crystal output (XOut) 2 I/O I P2[3] Crystal input (XIn) 3 I/O I P2[1] 4 IOHR I P1[7] I2C SCL, SPI ...

Page 10

QFN with USB Table 4. Pin Definitions - CY8C20396 PSoC Device Type Pin No. Name Digital Analog 1 I/O I P2[5] 2 I/O I P2[3] 3 I/O I P2[1] 4 IOHR I P1[7] I2C SCL, SPI SS 5 IOHR ...

Page 11

... QFN Table 5. Pin Definitions - CY8C20436, CY8C20446, [2, 3] CY8C20466 PSoC Device Type Pin Name No. Digital Analog 1 IOH I P0[1] Integrating input 2 I/O I P2[7] 3 I/O I P2[5] Crystal output (XOut) 4 I/O I P2[3] Crystal input (XIn) 5 I/O I P2[1] 6 I/O I P3[3] 7 I/O I P3[1] 8 IOHR I P1[7] I2C SCL, SPI SS 9 IOHR I P1[5] I2C SDA, SPI MISO ...

Page 12

QFN (with USB) Table 6. Pin Definitions - CY8C20496 PSoC Device Type Pin Name No. Digital Analog 1 IOH I P0[1] 2 I/O I P2[5] XTAL Out 3 I/O I P2[3] XTAL In 4 I/O I P2[1] 5 IOHR ...

Page 13

SSOP Table 7. Pin Definitions - CY8C20536, CY8C20546, [2] and CY8C20566 PSoC Device Name Description 1 IOH I P0[7] 2 IOH I P0[5] 3 IOH I P0[3] 4 IOH I P0[1] 5 I/O I P2[7] 6 I/O I P2[5] ...

Page 14

QFN Table 8. Pin Definitions - CY8C20636 PSoC Device Pin Name Description No connection 2 I/O I P2[7] 3 I/O I P2[5] Crystal output (XOut) 4 I/O I P2[3] Crystal input (XIn) 5 I/O I P2[1] ...

Page 15

QFN with USB Table 9. Pin Definitions - CY8C20646, CY8C20666 PSoC Device Pin Name Description No connection 2 I/O I P2[7] 3 I/O I P2[5] Crystal output (XOut) 4 I/O I P2[3] Crystal input (XIn) 5 ...

Page 16

QFN OCD The 48-pin QFN part is for the CY8C20066 On-Chip Debug (OCD) PSoC device. Note that this part is only used for in-circuit [4] debugging. Table 10. Pin Definitions - CY8C20066 PSoC Device Pin Name No. 1 OCDOE ...

Page 17

Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C20x36/46/66/96 PSoC devices. For the latest electrical specifications, confirm that you have the most recent data sheet by visiting the web at Figure 10. Voltage versus CPU ...

Page 18

Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 12. Absolute Maximum Ratings Symbol Description T Storage Temperature STG Vdd Supply Voltage Relative to Vss V DC Input Voltage ...

Page 19

DC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 14. DC Chip-Level Specifications Symbol Description Vdd Supply Voltage I Supply Current, IMO = 24 MHz DD24 I Supply Current, ...

Page 20

Table 15. 3.0V to 5.5V DC GPIO Specifications (continued) Symbol Description V High Output Voltage OH10 Port 1 Pins with LDO Enabled for 1.8V Out V Low Output Voltage OL V Input Low Voltage IL V Input High Voltage IH ...

Page 21

Table 16. 2.4V to 3.0V DC GPIO Specifications Symbol Description R Pull up Resistor PU V High Output Voltage OH1 Port Pins V High Output Voltage OH2 Port Pins V High Output Voltage OH3 ...

Page 22

Table 17. 1.71V to 2.4V DC GPIO Specifications (continued) Symbol Description V Input Hysteresis Voltage H I Input Leakage (Absolute Value Capacitive Load on Pins PIN Table 18.DC Characteristics – USB Interface Symbol Description Rusbi USB D+ Pull ...

Page 23

Comparator User Module Electrical Specifications The following table lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the entire device voltage and temperature operating range: –40°C <= TA <= 85°C, 1.71V <= Vdd <= 5.5V. ...

Page 24

DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 23. DC POR and LVD Specifications Symbol Description Vdd Value for PPOR Trip V PORLEV[1:0] = 00b, HPOR ...

Page 25

AC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 25. AC Chip-Level Specifications Symbol Description F CPU Frequency CPU F Internal Low Speed Oscillator Frequency 32K1 F Internal Main ...

Page 26

AC General Purpose IO Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 26. AC GPIO Specifications Symbol Description F GPIO Operating Frequency GPIO TRise23 Rise Time, Strong Mode, Cload = ...

Page 27

Table 27.AC Characteristics – USB Data Timings Symbol Description Tdrate Full speed data rate Tdjr1 Receiver data jitter tolerance Tdjr2 Receiver data jitter tolerance Tudj1 Driver differential jitter Tudj2 Driver differential jitter Tfdeop Source jitter for differential transition Tfeopt Source ...

Page 28

AC Programming Specifications SCLK (P1[1]) T RSCLK SDATA (P1[0]) T SSCLK The following table lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 32. AC Programming Specifications Symbol Description T Rise Time of SCLK ...

Page 29

AC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 33. AC Characteristics of the I2C SDA and SCL Pins Symbol F SCL Clock Frequency SCLI2C T Hold Time (repeated) ...

Page 30

Table 34. SPI Master AC Specifications Symbol Description F SCLK clock frequency SCLK DC SCLK duty cycle T MISO to SCLK setup time SETUP T SCLK to MISO hold time HOLD T SCLK to MOSI valid time OUT_VAL T MOSI ...

Page 31

Packaging Information This section illustrates the packaging specifications for the CY8C20x36/46/66/96 PSoC device, along with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a ...

Page 32

Document Number: 001-12696 Rev. *E Figure 16. 24-Pin (4x4 x 0.6 mm) QFN Figure 17. 32-Pin (5x5 x 0.6 mm) QFN CY8C20X36/46/66/96 001-13937 *B 001-42168 *C Page [+] Feedback ...

Page 33

BSC 0.008 0.0135 Important Notes For information on the preferred dimensions for mounting QFN packages, see the following Application Note at ■ http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. Pinned vias for thermal conduction are not required for the ...

Page 34

Thermal Impedances Table 36. Thermal Impedances per Package Package 16 QFN [13] 24 QFN [13] 32 QFN 48 SSOP [13] 48 QFN Solder Reflow Peak Temperature This table lists the minimum solder reflow peak temperature to achieve good solderability. Table ...

Page 35

Development Tool Selection Software PSoC Designer™ At the core of the PSoC development software suite is PSoC Designer, used to generate PSoC firmware applications. PSoC Designer is available free of charge at http://www.cypress.com/psocdesigner and includes a free C compiler. PSoC ...

Page 36

... USB 2.0 Cable ■ Accessories (Emulation and Programming) Table 38. Emulation and Programming Accessories Part Number Pin Package CY8C20236-24LKXI 16 QFN CY8C20246-24LKXI 16 QFN CY8C20336-24LQXI 24 QFN CY8C20346-24LQXI 24 QFN CY8C20396-24LQXI 24 QFN CY8C20436-24LQXI 32 QFN CY8C20446-24LQXI 32 QFN CY8C20466-24LQXI 32 QFN CY8C20496-24LQXI 32 QFN CY8C20536-24PVXI 48 SSOP CY8C20546-24PVXI 48 SSOP CY8C20566-24PVXI 48 SSOP CY8C20636-24LTXI 48 QFN ...

Page 37

... Reel) 24-Pin (4x4x0.6mm) QFN CY8C20396-24LQXI 24-Pin (4x4x0.6mm) QFN CY8C20396-24LQXIT (Tape and Reel) 32-Pin (5x5x0.6mm) QFN CY8C20436-24LQXI 32-Pin (5x5x0.6mm) QFN CY8C20436-24LQXIT (Tape and Reel) 32 Pin (5x5 x 0.6 mm) QFN CY8C20446-24LQXI 32 Pin (5x5 x 0.6 mm) QFN CY8C20446-24LQXIT (Tape and Reel) 32 Pin (5x5 x 0.6 mm) QFN CY8C20466-24LQXI 32 Pin (5x5 x 0 ...

Page 38

Document History Page Document Title: CY8C20x36/46/66/96 CapSense Document Number: 001-12696 Revision ECN Origin of Change ** 766857 HMT *A 1242866 HMT *B 2174006 AESA *C 2587518 TOF/JASM/MNU/ HMT *D 2649637 SNV/AESA *E 2700196 SNV/PYRS Document Number: 001-12696 Rev. *E Applications ...

Page 39

... Document Number: 001-12696 Rev. *E PSoC Designer™ trademark and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips ...

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