cy8c20111 Cypress Semiconductor Corporation., cy8c20111 Datasheet
cy8c20111
Related parts for cy8c20111
cy8c20111 Summary of contents
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... I C. The four key blocks that make up the CY8C20111 and CY8C20121 controllers are: a robust capacitive sensing core with high immunity against radiated and conductive noise, control registers with nonvolatile storage, configurable outputs, ...
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... Pinouts Figure 1. CY8C20111 Pin Diagram - 8 SOIC - 1 Button Table 1. Pin Definitions – 8 SOIC- 1 Button Pin No Name 1 VSS Ground 2 2 I2C SCL I C Clock 2 3 I2C SDA I C Data 4 CS0 CapSense Input Connect 6 DIG0 Digital Output Connect 8 VDD Supply Voltage Figure 2. CY8C20121 Pin Diagram – 8 SOIC- 2 Button Table 2. Pin Definitions – ...
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... Typical Circuits 4.1 Circuit-1: One Button and One LED 4.2 Circuit-2: One Button and One LED with I Note 1. The sensors are factory tuned to work with 1 mm plastic or glass overlay. Document Number: 001-53516 Rev. ** PRELIMINARY [ Interface CY8C20111, CY8C20121 Page [+] Feedback ...
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... Circuit-3: Two Buttons and Two LEDs with I 4.4 Circuit-4: Compatibility with 1.8V I Note < < < 2. 1.8V VDD_I2C VDD_CE and 2.4V VDD_CE Document Number: 001-53516 Rev. ** PRELIMINARY 2 C Interface 2 [2] C Signaling < 5.25V. CY8C20111, CY8C20121 Page [+] Feedback ...
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... Table 3 shows example for different CY8C20111, CY8C20121 I2C Pull UPs I2C BUS 2 C data 2 C addresses Bit Slave Address (in Hex) 0(W) 02 1(R) 03 0(W) 96 1(W) 97 Page [+] Feedback ...
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... Figure 3. Write ACK Time Representation Figure 4. Read ACK Time Representation A Data A Data Stop A Data Data CY8C20111, CY8C20121 2 C Master) must wait for a specific amount of Format for Register Write 2 C master initiates any data transfer with on page 7. Data A Stop N Stop Page [+] Feedback ...
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... CY8C20111, CY8C20121 Max Max ACK ACK Time in Time in Normal Setup Page No. [5] Mode (ms) Mode [5] (ms ...
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... Document Number: 001-53516 Rev. ** PRELIMINARY Executable Duration the Device is NOT Ac- Mode Setup/Normal Setup/Normal Setup/Normal Setup/Normal Setup/Normal Setup/Normal Setup Setup/Normal Setup/Normal Setup/Normal Setup/Normal Setup/Normal 2 C address. CY8C20111, CY8C20121 [5] cessible after ACK (in ms) 0 120 120 120 Page [+] Feedback ...
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... A bit set in this register sets the logic level of the output. 0 Logic ‘0’ 1 Logic ‘1’ Description These bits are used to enable CapSense inputs. 0 Disable CapSense input 1 Enable CapSense input CY8C20111, CY8C20121 1 0 W:01 DIG[ W:03 DIG[1: RW:01 CS[ RW:03 CS[1:0] Page [+] Feedback ...
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... Disable DIG output 1 Enable DIG output Description These bits are used to set the strong drive mode to DIG outputs. 0 Strong drive mode not set 1 Strong drive mode set CY8C20111, CY8C20121 1 0 RW:01 DIG[ RW:03 DIG [1: RW: RW:03 DM [1:0] ...
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... LOGICAL_OPR_INPUT0 [0] ENB CS0 OP_SEL_0 [0] LOGICAL_OPR_INPUTx [0] ENB CS0 LOGICAL_OPR_INPUTx [1] ENB CS1 INPUT SELECTION LOGIC Document Number: 001-53516 Rev. ** PRELIMINARY Figure 5. CY8C20111 Digital Logic Diagram OUTPUT_PORT [0] INVERSION LOGIC OP_SEL_0 [1] Figure 6. CY8C20121 Digital Logic Diagram A AND / OR Logic selection B S OP_SEL_x [0] CY8C20111, CY8C20121 A DIG0 AND / OR ...
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... This bit selects which operator should be used to compute logic operation. 0 Logic operator OR is used on inputs 1 Logic operator AND is used on inputs Description These bits selects the input for logic operation block. CY8C20111, CY8C20121 1 0 RW: 0 RW: 0 InvOp Operator 1 0 RW:01 CSL[ RW:01 CSL [1: RW:02 CSL [1:0] ...
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... These bits are used to set the noise threshold value RW:64 BLUT[7:0] Description These bits set the threshold that the bucket must reach for baseline to increment RW:A0 STLNG_TM[7:0] Description These bits are used to set the settling time value. CY8C20111, CY8C20121 Page [+] Feedback ...
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... Frequency of Operation 00 IMO 01 IMO/2 10 IMO/4 11 IMO/8 This bit is used to enable or disable sensor auto reset. 0 Disable Sensor auto reset 1 Enable Sensor auto reset RW:0A HYS[7:0] Description These bits are used to set the hysteresis value. CY8C20111, CY8C20121 Page [+] Feedback ...
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... These bits are used to set the debounce value RW:0A NNT[7:0] Description These bits are used to set the negative noise value RW:0A LBR[7:0] Description These bits are used to set the Low Baseline Reset value. CY8C20111, CY8C20121 Page [+] Feedback ...
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... Enable the average filter These bits are used to select the number of CapSense samples to average: Avg_Order[1:0] in Hex Description This bit sets the scan position. CY8C20111, CY8C20121 RW: 00 Avg_Order[1: communication Samples to Average RW: 0 ...
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... RW: 0A IDAC[7:0] Description These bit set the IDAC values address register (7Ch) access. The device I Description This bit gives the lock/unlock status Unlocked 1 Locked CY8C20111, CY8C20121 WPR: 0 I2CAL 2 C address should be modified by writing 2 C address. ...
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... Store or Write POR command. This bit indicates whether CapSense function is enabled or disabled. 0 Functionality of CapSense block is disabled 1 Functionality of CapSense block is enabled This bit indicates whether GP Output function is enabled or disabled. 0 Functionality of Digital output block is disabled 1 Functionality of Digital output block is enabled CY8C20111, CY8C20121 ...
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... These bits decide which CapSense button scan result are read. When writing to this register, the bitmask must contain only one bit set to ’1’, otherwise the data is discarded. CSBN [1:0] CapSense Button CY8C20111, CY8C20121 RW: 0 CSBN[ RW: 00 ...
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... [7:0] Description These bits represent the baseline value DIF [7:0] Description These bits represent the sensor difference count [7:0] Description These bits represent the raw count value. CY8C20111, CY8C20121 Page [+] Feedback ...
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... To define new POR defaults: ■ Write command 03h ■ Write 122 data bytes with new values of registers (use the _flash.iic file generated from s/w tool) ■ Write one CRC byte calculated as XOR of previous 122 data bytes CY8C20111, CY8C20121 BT_ST[ ...
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... A0h register, reading one byte returns the CSA scanning status. It returns the LVD_STOP_SCAN and STOP_SCAN bits. LVD_STOP_SCAN is bit 3 - Set when CSA is stopped because VCC is outside the valid operating range. STOP_SCAN is bit 2 - Set when CSA is stopped by the user by writing command 0x0A. CY8C20111, CY8C20121 Page [+] Feedback ...
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... Cut a hole in the sensor pad and use rear mountable LEDs. Refer Example PCB Layout Design with Two CapSense Buttons and Two LEDs Standard board thickness for CapSense FR4 based designs is 1.6 mm. CY8C20111, CY8C20121 Recommendations/Remarks on page 26. Page [+] Feedback ...
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... X: Button to ground clearance Y: Button to button clearance Document Number: 001-53516 Rev. ** PRELIMINARY Figure 7. Button Shapes Figure 8. Button Layout Design Figure 9. Recommended Via-hole Placement CY8C20111, CY8C20121 Page [+] Feedback ...
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... Example PCB Layout Design with Two CapSense Buttons and Two LEDs Document Number: 001-53516 Rev. ** PRELIMINARY Figure 10. Top Layer Figure 11. Bottom Layer CY8C20111, CY8C20121 Page [+] Feedback ...
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... Supply Voltage Variation ( Document Number: 001-53516 Rev. ** PRELIMINARY on page 7 and CapSense Express Commands Min Typ Max Units All layout best practices followed, properly tuned and noise free condition. ± 5% CY8C20111, CY8C20121 on page 8. I2C 4x Ack time is Notes Page [+] Feedback ...
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... – 0.5 – 0 – 0.5 – 0 –25 – +50 mA 2000 – – V Human body model ESD – – 200 mA Min Typ Max Unit –40 – +85 °C –40 – +100 °C CY8C20111, CY8C20121 Notes Notes Page [+] Feedback ...
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... Package and pin dependent. Temp = 25°C. k Ω 4 5.6 8 Min Typ Max Unit V – 2.36 2.40 V during startup or reset from watchdog. – 2.60 2.65 V CY8C20111, CY8C20121 Notes = 3.10V 25° Notes > 3.10V DD > 3.10V DD > 3.10V, maximum of DD Notes 2 C lines drive mode must be set to open Notes <2.9V and 3.1<V <3.6V ...
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... The device automatically reconfigures itself to work in 3.3V mode of operation. <2.4V The device goes into reset. <4.73V The scanning for CapSense parameters shuts down until the voltage returns to over 4.73V. CY8C20111, CY8C20121 Units Notes V mA – Erase/write cycles Years Result ...
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... HDSTAI2C t SUSTAI2C t Sr HIGHI2C CY8C20111, CY8C20121 Unit Notes 3.10V to 3.6V and 4.75V to DD 5.25V, 10 3.10V to 3.6V and 4.75V to DD 5.25V, 10% - 90% Unit Notes 2.4V to 2.90V, 10 2.4V to 2.90V, 10% - 90% DD ...
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... Set the read point to 82h Consecutive 6 reads gets baseline, difference count RD RD and raw count (all two byte each Set the read pointer Reading a byte gets status CapSense inputs CY8C20111, CY8C20121 Comment Page [+] Feedback ...
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... Part Number Family Code Technology Code CMOS Marketing Code Cypress Semiconductors Company ID Cypress Document Number: 001-53516 Rev. ** PRELIMINARY Operating CapSense Package Type Temperature Industrial Industrial Industrial Industrial CY8C20111, CY8C20121 CapSense Digital XRES Blocks Inputs Outputs Yes 1 1 Yes 1 1 Yes 2 ...
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... S08.15 STANDARD PKG. SZ08.15 LEAD FREE PKG. 8 SEATING PLANE 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.004[0.102] 0°~8° 0.0098[0.249] CY8C20111, CY8C20121 MAX. PART # 0.010[0.254] X 45° 0.016[0.406] 0.0075[0.190] 0.016[0.406] 0.0098[0.249] 0.035[0.889] 51-85066-*C ...
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... Document History Page Document Title: CY8C20111, CY8C20121 CapSense Express™ - One Button and Two Button Capacitive Controllers Document Number: 001-53516 Orig. of Rev. ECN. Change ** 2709248 SLAN/PYRS 16. Sales, Solutions, and Legal Information 16.1 Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress ...