ade7753 Analog Devices, Inc., ade7753 Datasheet

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... The ADE7753 contains an Active Energy register capable of holding more than 200 seconds of accumulated power at full load. Data is read from the ADE7753 via the serial interface. The ADE7753 also provides a pulse output (CF) with output frequency is proportional to the active power ...

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... PRELIMINARY TECHNICAL DATA ADE7753–SPECIFICATIONS Parameter ENERGY MEASUREMENT ACCURACY Measurement Bandwidth 1 Measurement Error on Channel 1 Channel 1 Range = 0.5V full-scale Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 Channel 1 Range = 0.25V full-scale Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 Channel 1 Range = 0.125V full-scale Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 1 Phase Error ...

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... Typically 2 max Typically 3 ADE7753ARS ADE7753ARSRL +2.1V EVAL-ADE7753EB * RS = Shrink Small Outline Package in tubes; RSRL = Shrink Small Outline Package in reel –3– ADE7753 pin IN/OUT = pull up resistor ORDERING GUIDE Package Option* RS-20 RS-20 ADE7753 evaluation board ...

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... PRELIMINARY TECHNICAL DATA ADE7753 ADE7753 TIMING CHARACTERISTICS Parameter A,B Versions Write timing 150 2 t 150 100 8 Read timing t 3 100 100 13 10 NOTES 1 Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with 5ns (10% to 90%) and timed from a voltage level of 1 ...

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... CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumu- late on the human body and test equipment and can discharge without detection. Although the ADE7753 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

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... ADE7753 Pin No. MNEMONIC 1 RESET Reset pin for the ADE7753. A logic low on this pin will hold the ADCs and digital circuitry (including the Serial Interface reset condition Digital power supply. This pin provides the supply voltage for the digital circuitry in DD the ADE7753. The supply voltage should be maintained at 5V ± ...

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... CLKIN or a crystal is being used Chip Select. Part of the four wire SPI Serial Interface. This active low logic input al- lows the ADE7753 to share the serial bus with several other devices. See ADE7753 Serial Interface Serial Clock Input for the synchronous serial interface. All Serial data transfers are synchronized to this clock— ...

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... PRELIMINARY TECHNICAL DATA ADE7753 Typical Performance Characteristics-ADE7753 TBD TPC 1— Error Reading (Gain=1) TBD TPC 2— Error Reading (Gain=4) TBD TPC 3— Error Reading (Gain=16) TBD TPC 4— Error Reading (Full-Scale input for Chan- nel 1=0.25V, Gain=4) TBD TPC 5— ...

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... PRELIMINARY TECHNICAL DATA ANALOG INPUTS The ADE7753 has two fully differential voltage input chan- nels. The maximum differential input voltage for input pairs V1P/V1N and V2P/V2N are ±0.5V. In addition, the maxi- mum signal level on analog inputs for V1P/V1N and V2P/ V2N are ±0.5V with respect to AGND. ...

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... The current signal needs to be recovered from the di/dt signal before it can be used. An integrator is therefore necessary to restore the signal to its original form. The ADE7753 has a built-in digital integrator to recover the current signal from the di/dt sensor. The digital integrator on Channel 1 is switched off by default when the ADE7753 is powered up ...

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... Antialias Filter. When the digital integrator is switched off, the ADE7753 can be used directly with a conventional current sensor such as current transformer (CT low resistance current shunt. ...

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... The ADE7753 also contains an on-chip power supply moni- tor. The Analog Supply ( continuously monitored DD by the ADE7753. If the supply is less than 4V ± 5% then the ADE7753 will go into an inactive state, i.e. no energy will be accumulated when the supply voltage is below 4V. This is useful to ensure correct device operation at power up and during power down ...

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... ADE7753 interrupt manage- ment using an MCU. At time t low indicating that one or more interrupt events have oc- curred in the ADE7753. The IRQ logic output should be tied to a negative edge triggered external interrupt on the MCU. On detection of the negative edge, the MCU should be configured to start executing its Interrupt Service Routine (ISR) ...

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... Figure 17– First Order Sigma-Delta ( A sigma-delta modulator converts the input signal into a continuous serial stream of 1's and 0 rate determined by the sampling clock. In the ADE7753 the sampling clock is equal to CLKIN/4. The 1-bit DAC in the feedback loop is driven by the serial data stream. The DAC output is sub- tracted from the input signal ...

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... Figure 19 —ADC and signal processing in Channel 1 ADC transfer function Below is an expression which relates the output of the LPF in the sigma-delta ADC to the analog input signal level. Both ADCs in the ADE7753 are designed to produce the same output code for the same input signal level. V Code ...

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... ADE7753 availability by going active low. The timing is shown in Figure 22. The 24-bit waveform samples are transferred from the ADE7753 one byte (8-bits time, with the most significant byte shifted out first. The 24-bit data word is right justified - see ADE7753 Serial Interface. ...

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... Channel 2 Figure 26 - Channel 2 RMS signal processing Channel 2 RMS offset compensation The ADE7753 incorporates a channel 2 RMS offset compen- 0.73dB sation register (VRMSOS). This is a 12-bit signed registers which can be used to remove offset in the channel 2 RMS calculation. An offset may exist in the RMS calculation due to input noises and dc offset in the input samples ...

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... The errors associated with phase mismatch are particularly noticeable at low power factors. The ADE7753 provides a means of digitally calibrating these small phase errors. The ADE7753 allows a small time delay or time advance to be introduced into the signal processing chain in order to compensate for small phase errors. Because the compensa- tion is in time, this technique should only be used for small phase errors in the range of 0.1° ...

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... P is referred to as the Active or Real Power. Note that the active power is equal to the dc component of the instanta- neous power signal p(t) in Equation 3 , i.e., VI. This is the relationship used to calculate active power in the ADE7753. The instantaneous power signal p(t) is generated by multiply- ing the current and voltage signals. The dc component of the instantaneous power signal is then extracted by LPF2 (Low Pass Filter) to obtain the active power information ...

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... Active Power Gain register contents are 7FFh, 000h and 800h. The Watt Gain (6) register is used to carry out power calibration in the ADE7753. As shown, the fastest integration time will occur when the Watt Gain register is set to maximum full scale, i.e., 7FFh. ...

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... Time = Time x WDIV WDIV=0 POWER OFFSET CALIBRATION The ADE7753 also incorporates an Active Power Offset register (APOS[15:0]). This is a signed 2’s complement 16- bit register which can be used to remove offsets in the active power calculation—see Figure 33. An offset may exist in the power calculation due to cross talk between channels on the PCB or in the IC itself ...

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... POSITIVE ONLY ACCUMULATION MODE In Positive Only Accumulation mode, the energy accumula- tion is done only for positive power, ignoring any occurrence of negative power above or below the no load threshold as shown in Figure 40. The ADE7753 is placed in positive only Active Energy No-load threshold Active Power ...

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... Interrupt Status Registers, PPOS and PNEG, show which transition has occurred. See ADE7753 Register Descriptions. NO LOAD THRESHOLD The ADE7753 includes a "no load threshold" feature that will eliminate any creep effects in the meter. accomplishes this by not accumulating energy if the multi- plier output is below the "no load threshold". This threshold is 0 ...

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... Complement) and power output is scaled by –50%. The Apparent Power is calculated with the Current and Voltage RMS values obtained in the RMS blocks of the ADE7753. Shown in Figure 44 is the maximum code (Hexadecimal) output range of the Apparent Power signal. Note that the output range changes depending on the contents of the Apparent Power Gain registers ...

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... When VADIV is set to a value different from 0, the integra- tion time varies as shown on Equation 23. Time = Time LINE APPARENT ENERGY ACCUMULATION The ADE7753 is designed with a special Apparent Energy accumulation mode which simplifies the calibration process. By using the on-chip zero-crossing detection, the ADE7753 accumulates the Apparent Power signal in the LVAENERGY register for an integral number of half cycles, as shown in Figure 47 ...

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... Divide registers contents equal to 1h/166h, the output frequency is given as 2797Hz / 358 = 3.905Hz. This setting has an error of -0.1%. Calibrating CF is made easy by using the Calibration mode on the ADE7753. The critical part of this approach is that the 2 fl line frequency needs to be exactly known. If this is not ...

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... Maximum ZXTOUT period SUSPENDING THE ADE7753 FUNCTIONALITY The analog and the digital circuit can be suspended sepa- rately. The analog portion of the ADE7753 can be suspended by setting the ASUSPEND bit (bit 4) of the Mode register to logic high See Mode Register. In suspend mode, all waveform samples from the ADCs will be set to zeros ...

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... Bringing CS high during a data transfer operation will abort the transfer and place the serial bus in a high impedance state. The CS logic input may be tied low if the ADE7753 is the only device on IN OUT the serial bus. However with CS tied low, all initiated data transfer operations must be fully completed, i ...

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... The LSBs of this byte contain the address of the register which read. The ADE7753 starts shifting out of the register data on the next rising edge of SCLK – see Figure 54. At this point the DOUT logic output leaves its high impedance state and starts driving the data bus ...

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... Enable register to logic zero. The Status register will continue to register an interrupt event even if disabled. However, the IRQ output will not be activated—see ADE7753 Interrupts. 0h The Interrupt Status register. This is an 8-bit read-only register. ...

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... SAGCYC register before the SAG pin is activated—see Line Voltage Sag Detection Channel 1 Peak Level threshold (current channel). This register sets the level of the current peak detection. If the channel 1 input exceeds this level, the PKI flag in the status register is set. –31– ADE7753 ...

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... R 8 bits ADE7753 REGISTER DESCRIPTIONS All ADE7753 functionality is accessed via the on-chip registers. Each register is accessed by first writing to the communications register and then transferring the register data. A full description of the serial interface protocol is given in the Serial Interface section of this data sheet. ...

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... PRELIMINARY TECHNICAL DATA Mode Register (09H) The ADE7753 functionality is configured by writing to the MODE register. Table VI below summarizes the functionality of each bit in the MODE register . Bit Bit Default Location Mnemonic Value Description The HPF (High Pass Filter) in Channel 1 is disabled when this bit is set. ...

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... The Status Register is used by the MCU to determine the source of an interrupt request (IRQ). When an interrupt event occurs in the ADE7753, the corresponding flag in the Interrupt Status register is set logic high. If the enable bit for this flag is logic one in the Interrupt Enable register, the IRQ logic output goes active low. When the MCU services the interrupt it must first carry out a read from the Interrupt Status Register to determine the source of the interrupt. Table VII: Interrupt Status Register, Reset Interrupt Status Register & ...

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... REV. PrF 10/02 OUTLINE DIMENSIONS Dimensions shown in inches and (mm) 20-Shrink Small Outline Package (RS-20) 0.295 (7.50) 0.271 (6.90 0.07 (1.78) 0.078 (1.98) PIN 1 0.066 (1.67) 0.068 (1.73 0.008 (0.203) SEATING 0.009 (0.229) (0.65) PLANE 0.002 (0.050) 0.005 (0.127) BSC –35– ADE7753 0.037 (0.94) 0.022 (0.559) ...

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... ADE7753 ADE7753 ERRATA (REV 1.0) The following is a list of known issues with the first revision of the ADE7753 silicon (rev 1.0). These issues will be resolved in the next version. Samples of this version of the silicon can be identified from the content of the DIEREV regsiter (Address 3Fh). The content of DIEREV register is 2 for Rev 1 ...

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... The definition of the SAGCYC a register has changed to full line cycles. LINECYC corrected to say 15 bits and remains half line cycles. 2. The PHCAL register description changed to reflect the Figure 13 new effective length and resolution of the register and default value of 0D. –37– ADE7753 ...

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