mc68hc908as60 Freescale Semiconductor, Inc, mc68hc908as60 Datasheet - Page 402
mc68hc908as60
Manufacturer Part Number
mc68hc908as60
Description
Mc68hc908as60 Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC908AS60.pdf
(454 pages)
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Timer Interface Module A (TIMA-6)
22.9.5 TIMA Channel Registers
Technical Data
CHxMAX — Channel x Maximum Duty Cycle Bit
These read/write registers contain the captured TIMA counter value of
the input capture function or the output compare value of the output
compare function. The state of the TIMA channel registers after reset is
unknown.
In input capture mode (MSxB–MSxA = 0:0), reading the high byte of the
TIMA channel x registers (TCHxH) inhibits input captures until the low
byte (TCHxL) is read.
In output compare mode (MSxB–MSxA 0:0), writing to the high byte of
the TIMA channel x registers (TCHxH) inhibits output compares and the
CHxF bit until the low byte (TCHxL) is written.
PTEx/TCHx
CHxMAX
When the TOVx bit is at logic 0, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100 percent.
As
it is set or cleared. The output stays at the 100 percent duty cycle level
until the cycle after CHxMAX is cleared.
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 22-8
OVERFLOW
Timer Interface Module A (TIMA-6)
Go to: www.freescale.com
COMPARE
PERIOD
OUTPUT
shows, the CHxMAX bit takes effect in the cycle after
Figure 22-8. CHxMAX Latency
OVERFLOW
COMPARE
OUTPUT
OVERFLOW
COMPARE
OUTPUT
MC68HC908AS60 — Rev. 1.0
OVERFLOW
COMPARE
OUTPUT
OVERFLOW
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