mc68hc705v12 Freescale Semiconductor, Inc, mc68hc705v12 Datasheet - Page 109

• Manufacturer Part Number: mc68hc705v12
• Description: M68hc05-based Mcu Hc05 Freescale Semiconductor
• Manufacturer: Freescale Semiconductor, Inc

10.6.2 Serial Peripheral Status Register
MC68HC705V12
—
Rev. 3.0
Address:
SPIF — SPI Transfer Complete Flag
WCOL — Write Collision Bit
MODF — Mode Fault Bit
Reset:
Read:
Write:
The serial peripheral data transfer flag bit is set upon completion of
data transfer between the processor and external device. If SPIF
goes high, and if SPIE is set, a serial peripheral interrupt is generated.
Clearing the SPIF bit is accomplished by reading the SPSR (with
SPIF set) followed by an access of the SPDR. Unless SPSR is read
(with SPIF set) first, attempts to write to SPDR are inhibited.
The write collision bit is set when an attempt is made to write to the
serial peripheral data register while data transfer is taking place. If
CPHA is 0, a transfer is said to begin when SS goes low and the
transfer ends when SS goes high after eight clock cycles on SCK.
When CPHA is 1, a transfer is said to begin the first time SCK
becomes active while SS is low and the transfer ends when the SPIF
flag gets set. Clearing the WCOL bit is accomplished by reading the
SPSR (with WCOL set) followed by an access to SPDR.
The mode fault flag indicates that there may have been a multi-master
conflict for system control and allows a proper exit from system
operation to a reset or default system state. The MODF bit is normally
clear and is set only when the master device has its SS pin set low.
Freescale Semiconductor, Inc.
For More Information On This Product,
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SPIF
Bit 7
0
Serial Peripheral Interface (SPI)
Go to: www.freescale.com
Figure 10-5. SPI Status Register (SPSR)
= Unimplemented
WCOL
6
0
5
0
0
MODF
4
0
3
0
0
Serial Peripheral Interface (SPI)
2
0
0
Advance Information
1
0
0
SPI Registers
Bit 0
0
0