mc68hc705v12 Freescale Semiconductor, Inc, mc68hc705v12 Datasheet - Page 110

• Manufacturer Part Number: mc68hc705v12
• Description: M68hc05-based Mcu Hc05 Freescale Semiconductor
• Manufacturer: Freescale Semiconductor, Inc

Serial Peripheral Interface (SPI)
10.6.3 Serial Peripheral Data Register
Advance Information
Address:
The serial peripheral data I/O register is used to transmit and receive
data on the serial bus. Only a write to this register will initiate
transmission/reception of another byte, and this will only occur in the
master device. At the completion of transmitting a byte of data, the SPIF
status bit is set in both the master and slave devices.
When the user reads the serial peripheral data I/O register, a buffer is
actually being read. The first SPIF must be cleared by the time a second
transfer of the data from the shift register to the read buffer is initiated or
an overrun condition will exist. In cases of overrun, the byte which
causes the overrun is lost.
A write to the serial peripheral data I/O register is not buffered and
places data directly into the shift register for transmission.
Reset:
Read:
Write:
Setting the MODF bit affects the internal serial peripheral interface
system in these ways:
Clearing the MODF bit is accomplished by reading the SPSR (with
MODF set), followed by a write to the SPCR. Control bits SPE and
MSTR may be restored by user software to their original state after
the MODF bit has been cleared. It is also necessary to restore the
port B DDR bits after a mode fault.
Freescale Semiconductor, Inc.
1. An SPI interrupt is generated if SPIE = 1.
2. The SPE bit is cleared, disabling the SPI.
3. The MSTR bit is cleared, thus forcing the device into the slave
For More Information On This Product,
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SPD7
mode.
Bit 7
Serial Peripheral Interface (SPI)
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Figure 10-6. SPI Data Register (SPDR)
SPD6
6
SPD5
5
Unaffected by reset
SPD4
4
SPD3
3
MC68HC705V12
SPD2
2
SPD1
1
—
Rev. 3.0
SPD0
Bit 0