mc68hc705v12 Freescale Semiconductor, Inc, mc68hc705v12 Datasheet - Page 146

• Manufacturer Part Number: mc68hc705v12
• Description: M68hc05-based Mcu Hc05 Freescale Semiconductor
• Manufacturer: Freescale Semiconductor, Inc

Byte Data Link Controller – Digital (BDLC–D)
14.5.1 Rx Digital Filter
14.5.1.1 Operation
Advance Information
The receiver section of the BDLC includes a digital low pass filter to
remove narrow noise pulses from the incoming message. An outline of
the digital filter is shown in
The clock for the digital filter is provided by the MUX interface clock (see
f
signal, the current state of the receiver physical interface (BDRxD) signal
is sampled. The BDRxD signal state is used to determine whether the
counter should increment or decrement at the next negative edge of the
clock signal.
The counter will increment if the input data sample is high but decrement
if the input sample is low. Therefore, the counter will thus progress either
up toward 15 if, on average, the BDRxD signal remains high or progress
down toward 0 if, on average, the BDRxD signal remains low.
When the counter eventually reaches the value 15, the digital filter
decides that the condition of the BDRxD signal is at a stable logic level
1 and the data latch is set, causing the filtered Rx data signal to become
a logic level 1. Furthermore, the counter is prevented from overflowing
and can be decremented only from this state.
BDLC
INTERFACE
INTERFACE
PHYSICAL
Freescale Semiconductor, Inc.
RX DATA
(BDRxD)
CLOCK
FROM
MUX
For More Information On This Product,
Byte Data Link Controller – Digital (BDLC–D)
parameter in
Figure 14-5. BDLC Rx Digital Filter Block Diagram
Go to: www.freescale.com
D
INPUT
SYNC
Q
Table
UP/DOWN
14-3). At each positive edge of the clock
Figure
4-BIT UP/DOWN COUNTER
14-5.
OUT
MC68HC705V12
D
LATCH
DATA
Q
RX DATA OUT
FILTERED
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Rev. 3.0