mc68hc705v12 Freescale Semiconductor, Inc, mc68hc705v12 Datasheet - Page 151

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mc68hc705v12

Manufacturer Part Number
mc68hc705v12
Description
M68hc05-based Mcu Hc05 Freescale Semiconductor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
14.5.3 J1850 VPW Symbols
MC68HC705V12
Rev. 3.0
IDLE — Idle Bus
Huntsinger’s variable pulse width modulation (VPW) is an encoding
technique in which each bit is defined by the time between successive
transitions and by the level of the bus between transitions (for instance,
active or passive). Active and passive bits are used alternately. This
encoding technique is used to reduce the number of bus transitions for
a given bit rate.
Each logic 1 or logic 0 contains a single transition and can be at either
the active or passive level and one of two lengths, either 64 s or 128 s
(t
previous bit. The start-of-frame (SOF), end-of-data (EOD), end-of-frame
(EOF), and inter-frame separation (IFS) symbols always will be encoded
at an assigned level and length. See
Each message will begin with an SOF symbol, an active symbol, and,
therefore, each data byte (including the CRC byte) will begin with a
passive bit, regardless of whether it is a logic 1 or a logic 0.
All VPW bit lengths stated in the following descriptions are typical values
at a 10.4-kbps bit rate. EOF, EOD, IFS, and IDLE, however, are not
driven J1850 bus states. They are passive bus periods observed by
each node’s CPU.
Logic 0
NOM
An idle condition exists on the bus during any passive period after
expiration of the IFS period (for example, 300 s). Any node sensing
an idle bus condition can begin transmission immediately.
A logic 0 is defined as either:
See
Freescale Semiconductor, Inc.
Byte Data Link Controller – Digital (BDLC–D)
For More Information On This Product,
– An active-to-passive transition followed by a passive period
– A passive-to-active transition followed by an active period
at 10.4 kbps baud rate), depending upon the encoding of the
Figure
64 s in length, or
128 s in length
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14-7(a).
Byte Data Link Controller – Digital (BDLC–D)
Figure
14-7.
BDLC MUX Interface
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