mc68hc705v12 Freescale Semiconductor, Inc, mc68hc705v12 Datasheet - Page 163

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mc68hc705v12

Manufacturer Part Number
mc68hc705v12
Description
M68hc05-based Mcu Hc05 Freescale Semiconductor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
14.6.5.1 4X Mode
14.6.5.2 Receiving a Message in Block Mode
14.6.5.3 Transmitting a Message in Block Mode
14.6.5.4 J1850 Bus Errors
MC68HC705V12
Rev. 3.0
The BDLC can exist on the same J1850 bus as modules which use a
special 4X (41.6 kbps) mode of J1850 variable pulse width modulation
(VPW) operation. The BDLC cannot transmit in 4X mode, but it can
receive messages in 4X mode, if the RX4XE bit is set in BCR2. If the
RX4XE bit is not set in the BCR2, any 4X message on the J1850 bus is
treated as noise by the BDLC and is ignored.
Although not a part of the SAE J1850 protocol, the BDLC does allow for
a special block mode of operation of the receiver. As far as the BDLC is
concerned, a block mode message is simply a long J1850 frame that
contains an indefinite number of data bytes. All other features of the
frame remain the same, including the SOF, CRC, and EOD symbols.
Another node wishing to send a block mode transmission must first
inform all other nodes on the network that this is about to happen. This
is usually accomplished by sending a special predefined message.
A block mode message is transmitted inherently by simply loading the
bytes one by one into the BDR until the message is complete. The
programmer should wait until the TDRE flag (see
Vector
The BDLC does not contain any predefined maximum J1850 message
length requirement.
The BDLC detects several types of transmit and receive errors which
can occur during the transmission of a message onto the J1850 bus.
Transmission Error
If the message transmitted by the BDLC contains invalid bits or
framing symbols on non-byte boundaries, this constitutes a
transmission error. When a transmission error is detected, the BDLC
Freescale Semiconductor, Inc.
Byte Data Link Controller – Digital (BDLC–D)
For More Information On This Product,
Register) is set prior to writing a new byte of data into the BDR.
Go to: www.freescale.com
Byte Data Link Controller – Digital (BDLC–D)
14.7.4 BDLC State
BDLC Protocol Handler
Advance Information

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